Skip to main content
  • Conference proceedings
  • © 2003

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings

Conference proceedings info: PATMOS 2003.

Buying options

eBook USD 84.99
Price excludes VAT (Canada)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 109.99
Price excludes VAT (Canada)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

This is a preview of subscription content, access via your institution.

Table of contents (68 papers)

  1. Front Matter

  2. Gate-Level Modeling and Design

    1. Analysis of High-Speed Logic Families

      • G. Privitera, Francesco Pessolano
      Pages 2-10
    2. Low Voltage, Double-Edge-Triggered Flip Flop

      • Pradeep Varma, Ashutosh Chakraborty
      Pages 11-20
    3. A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems

      • Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
      Pages 21-30
    4. State Encoding for Low-Power FSMs in FPGA

      • Luis Mengibar, Luis Entrena, Michael G Lorenz, Raúl Sánchez-Reillo
      Pages 31-40
  3. Low Level Modeling and Characterization

    1. Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies

      • Tim Schoenauer, Joerg Berthold, Christoph Heer
      Pages 41-50
    2. CMOS Gate Sizing under Delay Constraint

      • A. Verle, X. Michel, P. Maurine, N. Azémard, D. Auvergne
      Pages 60-69
    3. Process Characterisation for Low VTH and Low Power Design

      • E. Seebacher, G. Rappitsch, H. Höller
      Pages 70-79
    4. Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results

      • Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez
      Pages 80-89
  4. Interconnect Modeling and Optimization

    1. Effects of Temperature in Deep-Submicron Global Interconnect Optimization

      • M. R. Casu, M. Graziano, G. Piccinini, G. Masera, M. Zamboni
      Pages 90-100
    2. Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits

      • Jérôme Lescot, François J. R. Clément
      Pages 101-110
    3. Estimation of Crosstalk Noise for On-Chip Buses

      • Sampo Tuuna, Jouni Isoaho
      Pages 111-120
    4. A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization

      • M. Addino, M. R. Casu, G. Masera, G. Piccinini, M. Zamboni
      Pages 121-130
    5. Interconnect Driven Low Power High-Level Synthesis

      • A. Stammermann, D. Helms, M. Schulte, A. Schulz, W. Nebel
      Pages 131-140
  5. Asynchronous Techniques

    1. Bridging Clock Domains by Synchronizing the Mice in the Mousetrap

      • Joep Kessels, Ad Peeters, Suk-Jin Kim
      Pages 141-150
    2. Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization

      • Sonia López, Óscar Garnica, Ignacio Hidalgo, Juan Lanchares, Román Hermida
      Pages 151-160
    3. New GALS Technique for Datapath Architectures

      • Miloš Krstić, Eckhard Grass
      Pages 161-170
    4. Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders

      • João Leonardo Fragoso, Gilles Sicard, Marc Renaudin
      Pages 171-180

Other Volumes

  1. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

About this book

Welcome to the proceedings of PATMOS 2003. This was the 13th in a series of international workshops held in several locations in Europe. Over the years, PATMOS has gained recognition as one of the major European events devoted to power and timing aspects of integrated circuit and system design. Despite its signi?cant growth and development, PATMOS can still be considered as a very informal forum, featuring high-level scienti?c presentations together with open discussions and panel sessions in a free and relaxed environment. This year, PATMOS took place in Turin, Italy, organized by the Politecnico di Torino, with technical co-sponsorship from the IEEE Circuits and Systems Society and the generous support of the European Commission, as well as that of several industrial sponsors, including BullDAST, Cadence, Mentor Graphics, STMicroelectronics, and Synopsys. The objective of the PATMOS workshop is to provide a forum to discuss and investigate the emerging problems in methodologies and tools for the design of new generations of integrated circuits and systems. A major emphasis of the technical program is on speed and low-power aspects, with particular regard to modeling, characterization, design, and architectures.

Keywords

  • CAD design methods
  • CAD tools
  • CMOS
  • Circuit design
  • Flüssigkristallbildschirm
  • IC technology
  • Multimedia
  • Performance
  • Scheduling
  • architecture
  • computer architecture
  • low power design
  • low voltage memory
  • performance analysis
  • processor

Editors and Affiliations

  • Departamento de Tecnología Electrónica, Universidad de Sevilla Sevilla, (Spain)

    Jorge Juan Chico

  • Politecnico di Torino, Torino, Italy

    Enrico Macii

Bibliographic Information

Buying options

eBook USD 84.99
Price excludes VAT (Canada)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 109.99
Price excludes VAT (Canada)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions