A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512

  • Roar Lien
  • Tim Grembowski
  • Kris Gaj
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2964)


Hash functions are among the most widespread cryptographic primitives, and are currently used in multiple cryptographic schemes and security protocols, such as IPSec and SSL. In this paper, we investigate a new hardware architecture for a family of dedicated hash functions, including American standards SHA-1 and SHA-512. Our architecture is based on unrolling several message digest steps and executing them in one clock cycle. This modification permits implementing majority of dedicated hash functions with the throughput exceeding 1 Gbit/s using medium-size Xilinx Virtex FPGAs. In particular, our new architecture has enabled us to speed up the implementation of SHA-1 compared to the basic iterative architecture from 544 Mbit/s to 1 Gbit/s using Xilinx XCV1000. The implementation of SHA-512 has been sped up from 717 to 929 Mbit/s for Virtex FPGAs, and exceeded 1 Gbit/s for Virtex-E Xilinx FPGAs.


Hash Function Clock Cycle Critical Path Hardware Architecture Clock Period 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Roar Lien
    • 1
  • Tim Grembowski
    • 1
  • Kris Gaj
    • 1
  1. 1.ECE DepartmentGeorge Mason UniversityFairfaxUSA

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