Abstract
The design, implementation and system level performance of an efficient yet compact field programmable gate array (FPGA) based Secure Hash Algorithm 256 (SHA-256) processor is presented. On a Xilinx Virtex XCV300E-8 FPGA, the SHA-256 processor utilizes 1261 slices and has a throughput of 87 MB/s at 88 MHz. When measured on actual hardware operating at 66 MHz, it had a maximum measured system throughput of 53 MB/s.
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Ting, K.K., Yuen, S.C.L., Lee, K.H., Leong, P.H.W. (2002). An FPGA Based SHA-256 Processor. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_60
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DOI: https://doi.org/10.1007/3-540-46117-5_60
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