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Basics of Functional RAM Testing

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Multi-run Memory Tests for Pattern Sensitive Faults
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Abstract

The chapter presents an introduction to deterministic functional RAM testing. The memory chip model is given, and a set of traditional functional fault models (FFM) as well as basic march tests are discussed.

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References

  1. Abadir, M. S., and Reghbati, H. K. Functional testing of semiconductor random access memories. ACM Computing Surveys 15, 3 (Sept. 1983), 175–198.

    Article  Google Scholar 

  2. Adams, R., and Cooley, E. Analysis of a deceptive destructive read memory fault model and recommended testing. In Proceddings of the IEEE North Atlantic Test Workshop (1996).

    Google Scholar 

  3. Bushnell, M., and Agrawal, V. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Kluwer Academic Publishers, 2000.

    Google Scholar 

  4. Cheng, K.-L., Tsai, M.-F., and Wu, C.-W. Neighborhood pattern sensitive fault testing and diagnostics for random access memories. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 21, 11 (2002), 1328–1336.

    Article  Google Scholar 

  5. Cockburn, B. F., and Sat, Y. F. N. A transparent built-in self-test scheme for detecting single v-coupling faults in RAMs. In Proceedings of the IEEE International Workshop on Memory Technology, Design, and Test (Aug. 1994), pp. 119–124.

    Google Scholar 

  6. Dekker, R., Beenker, F., and Thijssen, L. Fault modeling and test algorithm development for static random access memories. In Proceedings of the IEEE International Test Conference (1988), ITC’88, pp. 343–352.

    Google Scholar 

  7. Dekker, R., Beenker, F., and Thijssen, L. A realistic fault model and test algorithms for static random access memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9, 6 (June 1990), 567–572.

    Article  Google Scholar 

  8. Demidenko, S., van de Goor, A., Henderson, S., and Knoppers, P. Simulation and development of short transparent tests for RAM. In Proceedings of the 10 th Asian Test Symposium (2001), ATS’01, pp. 164–169.

    Google Scholar 

  9. Hamdioui, S., Taouil, M., and Haron, N. Z. Testing open defects in memristor-based memories. IEEE Transactions on Computers 64, 1 (2015), 247–259.

    Article  MathSciNet  Google Scholar 

  10. Hellebrand, S., Wunderlich, H.-J., and Yarmolik, V. N. Symmetric transparent BIST for RAMs. In Proceedings of the Conference on Design, Automation and Test in Europe (New York, NY, USA, 1999), DATE’99, ACM, pp. 702–707.

    Google Scholar 

  11. Karpovski, M., and Yarmolik, V. Transparent memory BIST. In Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing (1994), MTDT’94, pp. 106–111.

    Google Scholar 

  12. Karpovsky, M. G., Goor, A. J. v. d., and Yarmolik, V. N. Pseudo-exhaustive word-oriented DRAM testing. In Proceedings of the European conference on Design and Test (Washington, DC, USA, 1995), EDTC’95, IEEE Computer Society, p. 126.

    Google Scholar 

  13. Karpovsky, M. G., and Yarmolik, V. N. Transparent memory testing for pattern-sensitive faults. In Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years (1994), ITC’94, IEEE Computer Society, pp. 860–869.

    Google Scholar 

  14. Kim, H.-S., and Kang, S. DPSC SRAM transparent test algorithm. In Proceedings of the 11 th Asian Test Symposium (Nov. 2002), ATS’02, pp. 145–150.

    Google Scholar 

  15. Knaizuk, J., and Hartman, C. An optimal algorithm for testing stuck-at faults in random access memories. IEEE Transactions on Computers C26, 11 (1977), 1141–1144.

    Article  MathSciNet  Google Scholar 

  16. Li, J.-F., Tseng, T.-W., and Wey, C.-L. An efficient transparent test scheme for embedded word-oriented memories. In Proceedings of the Design, Automation and Test in Europe (Mar. 2005), vol. 1 of DATE’05, pp. 574–579.

    Google Scholar 

  17. Marinescu, M. Simple and efficient algorithms for functional RAM testing. In Proceedings of the International Test Conference (1982), ITC’82.

    Google Scholar 

  18. Mikitjuk, V., and Yarmolik, V. N. RAM testing algorithm for detection linked coupling faults. In Proceedings of the Computer-Aided Design of Discrete Devices (Minsk-Szczecin, 1995), pp. 145–150.

    Google Scholar 

  19. Nair, R. Comments on “an optimal algorithm for testing stuck-at faults in random access memories”. IEEE Transactions on Computers C-28, 3 (1979), 258–261.

    Article  Google Scholar 

  20. Nair, R., Thatte, S. M., and Abraham, J. A. Efficient algorithms for testing semiconductor random-access memories. IEEE Transactions on Computers 27, 6 (1978), 572–576.

    Article  MathSciNet  Google Scholar 

  21. Nicolaidis, M. Transparent BIST for RAMs. In Proceedings of the IEEE International Test Conference, Discover the New World of Test and Design (Baltimore, Maryland, USA, Sept. 1992), ITS’92, IEEE Computer Society, pp. 598–607.

    Google Scholar 

  22. Nicolaidis, M. Theory of transparent BIST for RAMs. IEEE Transactions on Computers 45, 10 (1996), 1141–1156.

    Article  Google Scholar 

  23. Niggemeyer, D., Otterstedt, J., and Redeker, M. Detection of non classical memory faults using degrees of freedom in march testing. In Proceedings of the 11th IEEE International Workshop on Memory Technology, Design and Testing (Potsdam, 1999), pp. 111–119.

    Google Scholar 

  24. Niggemeyer, D., Rudnick, E. M., and Redeker, M. Diagnostic testing of embedded memories based on output tracing. In Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing (2000), MTDT’00, IEEE Computer Society, pp. 113–118.

    Google Scholar 

  25. Papachristou, C. A., and Sahgal, N. B. An improved method for detecting functional faults in semiconductor random access memories. IEEE Transactions on Computers, 2 (1985), 110–116.

    Article  Google Scholar 

  26. Rajski, J., and Tyszer, J. Arithmetic built-in self-test for embedded systems. Prentice-Hall, Inc., Upper Saddle River, NJ, USA, 1998.

    Google Scholar 

  27. Suk, D., and Reddy, S. A march test for functional faults in semiconductor random access memories. IEEE Transactions on Computers 30 (1981), 982–985.

    Article  Google Scholar 

  28. Thaller, K., and Steininger, A. A transparent online memory test for simultaneous detection of functional faults and soft errors in memories. IEEE Transactions on Reliability 52, 4 (Dec. 2003), 413–422.

    Article  Google Scholar 

  29. Thatte, S., and Abraham, J. Testing of semiconductor random access memories. Proceedings of the Annual International Conference on Fault-Tolerant Computing (1977), 81–87.

    Google Scholar 

  30. van de Goor, A., Gaydadjiew, G., Yarmolik, V., and Mikitjuk, V. March LA: A test for linked memory faults. In Proceedings of the European Design and Test Conference (1997), ED&TC’97.

    Google Scholar 

  31. van de Goor, A. J. Testing Semiconductor Memories: Theory and Practice. John Wiley & Sons, Chichester, England, 1991.

    Google Scholar 

  32. van de Goor, A. J., Gaydadjiev, G. N., Mikitjuk, V. G., and Yarmolik, V. N. March LR: a test for realistic linked faults. In Proceedings of the 14 th VLSI Test Symposium (Apr. 1996), pp. 272–280.

    Google Scholar 

  33. van de Goor, A. J., Gaydadjiew, G., Yarmolik, V., and Mikitjuk, V. Memory tests and their fault coverage into a new perspective, resulting into a new test. In Proceedings of the Semiconductor Technical Symposium on Test Technology (Jan. 1996), SEMICON’96, pp. 67–75.

    Google Scholar 

  34. van de Goor, A. J., and Verruijt, C. A. An overview of deterministic functional RAM chip testing. ACM Computing Surveys 22, 1 (Mar. 1990), 5–33.

    Article  Google Scholar 

  35. Voyiatzis, I., Efstathiou, C., and Sgouropoulou, C. Transparent testing for intra-word memory faults. In Proceedings of the 8 th IEEE Design and Test Symposium (Dec. 2013), pp. 1–2.

    Google Scholar 

  36. Yarmolik, V. N. Contents independent RAM built in self test and diagnoses based on symmetric transparent algorithm. In Proceedings of the 3 rd Workshop on Design and Diagnostics of Electronic Circuits and Systems (Smolenice, Slovakia, 2000), DDECS’00, IEEE Computer Society, pp. 220–227.

    Google Scholar 

  37. Yarmolik, V. N., Klimets, Y., and Demidenko, S. March PS(23N) test for DRAM pattern-sensitive faults. In Proceedings of the 7 th Asian Test Symposium (1998), ATS’98, IEEE Computer Society, pp. 354–357.

    Google Scholar 

  38. Zankovich, A. P., Yarmolik, V. N., and Sokol, B. Automatic generation of symmetric transparent march memory tests. In Proceedings of the 7 th International Conference The Experience of Designing and Application of CAD Systems in Microelectronics, 2003 (Feb. 2003), CADSM’03, pp. 226–229.

    Google Scholar 

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Mrozek, I. (2019). Basics of Functional RAM Testing. In: Multi-run Memory Tests for Pattern Sensitive Faults. Springer, Cham. https://doi.org/10.1007/978-3-319-91204-2_2

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  • DOI: https://doi.org/10.1007/978-3-319-91204-2_2

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  • Print ISBN: 978-3-319-91203-5

  • Online ISBN: 978-3-319-91204-2

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