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IP FSM Watermarking

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Foundations of Hardware IP Protection

Abstract

Hardware design reuse has been the viable solution to deal with the ever-increasing logic density in the semiconductor industry. For instance, an application-specific integrated circuit (ASIC) architecture can be designed using previously designed subcomponents or subsystems.

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Acknowledgement

The work presented in this paper was realized in the frame of the SALWARE project number ANR-13-JS03-0003 supported by the French” Agence Nationale de la Recherche” and by the French “Fondation de Recherche pour l’Aéronautique et l’Espace”.

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Authors and Affiliations

  1. Computer Science Department, Kennesaw State University, Marietta, GA, 30060, USA

    Edward Jung

  2. Laboratoire Hubert Curien, CNRS UMR 5516, Université Jean Monnet, 42000, Saint-Etienne, France

    Lilian Bossuet

Authors
  1. Edward Jung
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  2. Lilian Bossuet
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Correspondence to Edward Jung .

Editor information

Editors and Affiliations

  1. Laboratoire Hubert Curien, Jean Monnet University, Saint-Etienne, France

    Lilian Bossuet

  2. Laboratoire LIRMM, Université de Montpellier 2, Montpellier, France

    Lionel Torres

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Jung, E., Bossuet, L. (2017). IP FSM Watermarking. In: Bossuet, L., Torres, L. (eds) Foundations of Hardware IP Protection. Springer, Cham. https://doi.org/10.1007/978-3-319-50380-6_4

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  • DOI: https://doi.org/10.1007/978-3-319-50380-6_4

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-50378-3

  • Online ISBN: 978-3-319-50380-6

  • eBook Packages: EngineeringEngineering (R0)

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