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Impact of Two-Step Recessed SiGe S/D Engineering for Advanced pMOSFETs of 32 nm Technology Node and Beyond

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Simulation of Semiconductor Processes and Devices 2007

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Abstract

The two-step recessed SiGe Source/Drain (S/D) structure, which is one of the embedded SiGe S/D engineering techniques, is a leading candidate for advanced pMOSFETs from the viewpoint of good roll-off characteristics and high channel strain. In this paper, we reveal the merits of this technology for the application to the 32 nm technology node, including the methodology for suppressing the layout effect by TCAD analysis.

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References

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Author information

Authors and Affiliations

  1. System LSI Division, Center for Semiconductor R&D, Toshiba Corporation Semiconductor Company, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan

    N. Yasutake

  2. Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan

    I. Mizushima

Authors
  1. N. Kusunoki
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  2. N. Yasutake
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  3. M. Awano
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  4. I. Mizushima
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  5. H. Yoshimura
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  6. S. Yamada
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  7. F. Matsuoka
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Editor information

Editors and Affiliations

  1. Institut für Mikroelektronik, Technische Universität Wien, Vienna, Austria

    Tibor Grasser  & Siegfried Selberherr  & 

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© 2007 Springer-Verlag Wien

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Cite this paper

Kusunoki, N. et al. (2007). Impact of Two-Step Recessed SiGe S/D Engineering for Advanced pMOSFETs of 32 nm Technology Node and Beyond. In: Grasser, T., Selberherr, S. (eds) Simulation of Semiconductor Processes and Devices 2007. Springer, Vienna. https://doi.org/10.1007/978-3-211-72861-1_29

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  • DOI: https://doi.org/10.1007/978-3-211-72861-1_29

  • Publisher Name: Springer, Vienna

  • Print ISBN: 978-3-211-72860-4

  • Online ISBN: 978-3-211-72861-1

  • eBook Packages: EngineeringEngineering (R0)

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