Skip to main content
SpringerLink
Log in

An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits

  • Conference paper
  • First Online:
Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC 2023)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 14251))

Included in the following conference series:

  • 663 Accesses

Abstract

In the last decade, resistive random-access memory (RRAM) has been used in designing field-programmable gate arrays (FPGAs). The non-volatility of RRAM has made it a promising substitute for the traditional static random-access memory (SRAM) in emerging non-volatile FPGAs. Most use cases for RRAM in these FPGAs are restricted to the utilization in routing infrastructures and as a one-to-one substitute for the SRAM memory cells in building FPGA lookup tables (LUTs). In contrast, other FPGA building blocks remain the same. These approaches do not fully embrace RRAM as an emerging circuit element beyond memory. In this paper, we introduce an almost fully RRAM-based LUT design. Our design approach relies on RRAM implementing arbitrary Boolean logic in disjunctive normal form. The unique properties of RRAM crossbars are utilized to effectively integrate address decoder and memory in a single crossbar structure, reducing the amount of auxiliary CMOS components. The simulation results show that our RRAM-based LUT design exhibits low energy requirements at sub-picojoule consumption for read operations. Furthermore, it can achieve fast operations at more than 2.5 GHz for read accesses. To show the practicality and usability of our design, we also present an example application.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 59.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 74.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Almurib, H.A., et al.: A memristor-based LUT for FPGAs. In: The 9th IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), pp. 448–453 (2014)

    Google Scholar 

  2. Bazzi, H., et al.: RRAM-based non-volatile SRAM cell architectures for ultra-low-power applications. Analog Integr. Circ. Sig. Process 106(2), 351–361 (2021)

    Article  Google Scholar 

  3. Cadence Design System Inc: GPDK045 - 45nm CMOS 11M/2P generic PDK (2022)

    Google Scholar 

  4. Chen, Y.C., et al.: A novel peripheral circuit for RRAM-based LUT. In: 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1811–1814 (2012)

    Google Scholar 

  5. Chua, L.: Memristor-the missing circuit element. IEEE Trans. Circ. Theory 18(5), 507–519 (1971)

    Article  Google Scholar 

  6. Cong, J., Xiao, B.: MRFPGA: a novel FPGA architecture with memristor-based reconfiguration. In: 2011 IEEE/ACM International Symposium on Nanoscale Architectures, pp. 1–8 (2011)

    Google Scholar 

  7. Cong, J., Xiao, B.: FPGA-RPI: a novel FPGA architecture with RRAM-based programmable interconnects. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(4), 864–877 (2014)

    Google Scholar 

  8. De Nil, M., et al.: Ultra low power ASIP design for wireless sensor nodes. In: 2007 14th IEEE International Conference on Electronics, Circuits and Systems, pp. 1352–1355. IEEE (2007)

    Google Scholar 

  9. Gaillardon, P.E., et al.: GMS: generic memristive structure for non-volatile FPGAS. In: 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 94–98. IEEE (2012)

    Google Scholar 

  10. Giacomin, E., Gaillardon, P.E.: A resistive random access memory Addon for the NCSU FreePDK 45 nm. IEEE Trans. Nanotechnol. 18, 68–72 (2018)

    Article  Google Scholar 

  11. Guan, X., et al.: A spice compact model of metal oxide resistive switching memory with variations. IEEE Electron Device Lett. 33(10), 1405–1407 (2012)

    Article  Google Scholar 

  12. Guo, Y., et al.: A compact memristor-CMOS hybrid look-up-table design and potential application in FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12), 2144–2148 (2017)

    Article  Google Scholar 

  13. Kambayashi, Y.: Logic design of programmable logic arrays. IEEE Trans. Comput. 28(09), 609–617 (1979)

    Article  MathSciNet  MATH  Google Scholar 

  14. Kim, K.H., et al.: A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. Nano Lett. 12(1), 389–395 (2012)

    Article  Google Scholar 

  15. Kumar, T.N., et al.: A novel design of a memristor-based look-up table (LUT) for FPGA. In: 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 703–706 (2014)

    Google Scholar 

  16. Kvatinsky, S., et al.: Memristor-based material implication (IMPLY) logic: design principles and methodologies. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2054–2066 (2013)

    Google Scholar 

  17. Kvatinsky, S., et al.: Magic-memristor-aided logic. IEEE Trans. Circuits Syst. II Express Briefs 61(11), 895–899 (2014)

    Google Scholar 

  18. Lin, W.P., et al.: A nonvolatile look-up table using ReRAM for reconfigurable logic. In: 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 133–136. IEEE (2014)

    Google Scholar 

  19. Nguyen, H.A.D., et al.: A classification of memory-centric computing. ACM J. Emerg. Technol. Comput. Syst. (JETC) 16(2), 1–26 (2020)

    Article  MathSciNet  Google Scholar 

  20. Ochi, H., et al.: Via-switch FPGA: highly dense mixed-grained reconfigurable architecture with overlay via-switch crossbars. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(12), 2723–2736 (2018)

    Google Scholar 

  21. Pellegrino, L., et al.: Multistate memory devices based on free-standing VO2/TIO2 microstructures driven by joule self-heating. Adv. Mater. 24(21), 2929–2934 (2012)

    Article  Google Scholar 

  22. Rai, S., et al.: A survey of FPGA logic cell designs in the light of emerging technologies. IEEE Access 9, 91564–91574 (2021)

    Article  Google Scholar 

  23. Sampath, M., et al.: Hybrid CMOS-memristor based FPGA architecture. In: 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), pp. 1–6 (2015)

    Google Scholar 

  24. Strukov, D.B., et al.: The missing memristor found. Nature 453(7191), 80–83 (2008)

    Article  Google Scholar 

  25. Tang, X., et al.: A high-performance low-power near-VT RRAM-based FPGA. In: 2014 International Conference on Field-Programmable Technology (FPT), pp. 207–214 (2014)

    Google Scholar 

  26. Tang, X., et al.: Circuit designs of high-performance and low-power RRAM-based multiplexers based on 4T(ransistor)1R(RAM) programming structure. IEEE Trans. Circuits Syst. I Regul. Pap. 64(5), 1173–1186 (2017)

    Article  Google Scholar 

  27. Tang, X., et al.: Post-P &R performance and power analysis for RRAM-based FPGAS. IEEE J. Emerg. Sel. Topics Circ. Syst. 8(3), 639–650 (2018)

    Article  Google Scholar 

  28. Tang, X., et al.: A RRAM-based FPGA for energy-efficient edge computing. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 144-a-144-f (2020)

    Google Scholar 

  29. Tsekoura, I., et al.: An evaluation of energy efficient microcontrollers. In: 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp. 1–5. IEEE (2014)

    Google Scholar 

  30. Xie, L., et al.: Non-volatile look-up table based FPGA implementations. In: 2016 11th International Design & Test Symposium (IDT), pp. 165–170. IEEE (2016)

    Google Scholar 

  31. Xing, J., Serb, A., Khiat, A., Berdan, R., Xu, H., Prodromakis, T.: An FPGA-based instrument for EN-Masse RRAM characterization with ns pulsing resolution. IEEE Trans. Circuits Syst. I Regul. Pap. 63(6), 818–826 (2016)

    Article  MathSciNet  MATH  Google Scholar 

  32. Xu, C., et al.: Design implications of memristor-based RRAM cross-point structures. In: 2011 Design, Automation & Test in Europe, pp. 1–6. IEEE (2011)

    Google Scholar 

  33. Zahoor, F., et al.: Resistive random access memory (RRAM): an overview of materials, switching mechanism, performance, multilevel cell (MLC) storage, modeling, and applications. Nanoscale Res. Lett. 15(1), 1–26 (2020)

    Article  Google Scholar 

  34. Zhou, Y.X., et al.: Nonvolatile reconfigurable sequential logic in a HFO 2 resistive random access memory array. Nanoscale 9(20) (2017)

    Google Scholar 

Download references

Acknowledgments

This work has been supported by DAIS (https://dais-project.eu/), which has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 101007273. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Sweden, Spain, Portugal, Belgium, Germany, Slovenia, Czech Republic, Netherlands, Denmark, Norway, and Turkey.

Author information

Authors and Affiliations

  1. Institute of Computer Engineering (ITI), University of Lübeck, Ratzeburger Allee 160, 23562, Lübeck, Germany

    Philipp Grothe, Saleh Mulhem & Mladen Berekovic

Authors
  1. Philipp Grothe
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Saleh Mulhem
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mladen Berekovic
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Philipp Grothe .

Editor information

Editors and Affiliations

  1. Università degli Studi di Sassari, Sassari, Italy

    Francesca Palumbo

  2. Aristotle University of Thessaloniki, Thessaloniki, Greece

    Georgios Keramidas

  3. University of Peloponnese, Patras, Greece

    Nikolaos Voros

  4. University of Porto, Porto, Portugal

    Pedro C. Diniz

Rights and permissions

Reprints and permissions

Copyright information

© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Grothe, P., Mulhem, S., Berekovic, M. (2023). An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits. In: Palumbo, F., Keramidas, G., Voros, N., Diniz, P.C. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2023. Lecture Notes in Computer Science, vol 14251. Springer, Cham. https://doi.org/10.1007/978-3-031-42921-7_22

Download citation

  • DOI: https://doi.org/10.1007/978-3-031-42921-7_22

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-42920-0

  • Online ISBN: 978-3-031-42921-7

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation