Skip to main content
SpringerLink
Log in

Nonvolatile Memory Technologies: Characteristics, Deployment, and Research Challenges

  • Chapter
  • First Online:
Frontiers of Quality Electronic Design (QED)

Abstract

Nonvolatile memory (NVM) is a class of memory that exhibits persistence, similar to secondary memory, while providing access speeds at least an order of two magnitudes faster. In this area, phase change memory (PCM), spin-transfer torque random access memory (STT-RAM), and resistive RAM (ReRAM) have emerged as the major contenders for commercial and industrial use. With the enormous amount of data being generated, most recent applications demand huge memory footprints, large bandwidth, low energy consumption, and low price. Conventional DRAM-based memories face several issues, such as scalability and high static power consumption. Hence there is a necessity to build alternative memory devices to satisfy the demands of new applications. In this regard, NVMs are gaining prominence these days. This chapter gives a complete overview of the NVM devices, including characteristics, deployment, and challenges in integrating them at different levels of the memory hierarchy.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 79.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 99.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 129.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. Agarwal, S., Kapoor, H.K.: Improving the lifetime of non-volatile cache by write restriction. IEEE Trans. Comput. 68(9), 1297–1312 (2019). https://doi.org/10.1109/TC.2019.2892424

    Article  MathSciNet  MATH  Google Scholar 

  2. Akram, A., Sawalha, L.: A survey of computer architecture simulation techniques and tools. IEEE Access. 7, 78120–78145 (2019). https://doi.org/10.1109/ACCESS.2019.2917698

    Article  Google Scholar 

  3. Aswathy, N., Sivamangai, N.: Future nonvolatile memory technologies: challenges and applications. In: 2021 2nd International Conference on Advances in Computing, Communication, Embedded and Secure Systems (ACCESS), pp. 308–312 (2021). https://doi.org/10.1109/ACCESS51619.2021.9563288

  4. Aziza, H., Hamdioui, S., Fieback, M., Taouil, M., Moreau, M.: Density enhancement of RRAMS using a reset write termination for MLC operation. In: 2021 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1877–1880 (2021). https://doi.org/10.23919/DATE51398.2021.9473967

  5. Bahn, H., Cho, K.: Implications of NVM based storage on memory subsystem management. Appl. Sci. 10(3) (2020). Retrieved from https://www.mdpi.com/2076-3417/10/3/999, https://doi.org/10.3390/app10030999

  6. Banerjee, W.: Challenges and applications of emerging nonvolatile memory devices. Electronics 9(6) (2020). Retrieved from https://www.mdpi.com/2079-9292/9/6/1029, https://doi.org/10.3390/electronics9061029

  7. Baudry, L., Lukyanchuk, I., Vinokur, V.M.: Ferroelectric symmetry-protected multibit memory cell. Sci. Rep. 7(1), 42196 (2017, February 08). Retrieved from https://doi.org/10.1038/srep42196

  8. Bittman, D., Alvaro, P., Mehra, P., Long, D.D.E., Miller, E.L.: Twizzler: a data-centric OS for non-volatile memory. In: 2020 USENIX Annual Technical Conference (USENIX ATC 20) (2020, July)

    Google Scholar 

  9. Bojnordi, M.N., Ipek, E.: Memristive Boltzmann machine: a hardware accelerator for combinatorial optimization and deep learning. In: 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 1–13 (2016, March). https://doi.org/10.1109/HPCA.2016.7446049

  10. Bolotin, E., Nellans, D., Villa, O., O’Connor, M., Ramirez, A., Keckler, S.W.: Designing efficient heterogeneous memory architectures. IEEE Micro. 35(4), 60–68 (2015)

    Article  Google Scholar 

  11. Burr, G.W., Shelby, R.M., Sidler, S., di Nolfo, C., Jang, J., Boybat, I., et al.: Experimental demonstration and tolerancing of a large-scale neural network (165 000 synapses) using phase-change memory as the synaptic weight element. IEEE Trans. Electron Devices. 62(11), 3498–3507 (2015, Nov). https://doi.org/10.1109/TED.2015.2439635

    Article  Google Scholar 

  12. Cai, Y., Lin, Y., Xia, L., Chen, X., Han, S., Wang, Y., Yang, H.: Long live time: improving lifetime and security for NVM-based training-in-memory systems. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 39(12), 4707–4720 (2020). https://doi.org/10.1109/TCAD.2020.2977079

    Article  Google Scholar 

  13. Chen, Y.: RERAM: history, status, and future. IEEE Trans. Electron Devices. 67(4), 1420–1433 (2020). https://doi.org/10.1109/TED.2019.2961505

    Article  Google Scholar 

  14. Chen, Z., Gao, B., Zhou, Z., Huang, P., Li, H., Ma, W., … Chen, H.: Optimized learning scheme for grayscale image recognition in a rram based analog neuromorphic system. In: 2015 IEEE International Electron Devices Meeting (IEDM), pp. 17.7.1–17.7.4 (2015, December) https://doi.org/10.1109/IEDM.2015.7409722

  15. Chen, X., Wang, J., Zhou, J.: Promoting MLC STT-ram for the future persistent memory system. In: 2017 IEEE 15th International Conference on Dependable, Autonomic and Secure Computing, 15th International Conference on Pervasive Intelligence and Computing, 3rd International Conference on Big Data Intelligence and Computing and Cyber Science and Technology Congress (DASC/PICOM/ Datacom/ Cyberscitech), pp. 1180–1185 (2017). https://doi.org/10.1109/DASC-PICom-DataCom-CyberSciTec.2017.189

  16. Chi, P., Li, S., Xu, C., Zhang, T., Zhao, J., Liu, Y., … Xie, Y.: Prime: a novel processing-in-memory architecture for neural network computation in RERAM-based main memory. In: Proceedings of the 43rd International Symposium on Computer Architecture, pp. 27–39. IEEE Press, Piscataway (2016). Retrieved from https://doi.org/10.1109/ISCA.2016.13

  17. Chiu, C.-H., Huang, C.-W., Hsieh, Y.-H., Chen, J.-Y., Chang, C.-F., Chu, Y.-H., Wu, W.-W.: In-situ tem observation of multilevel storage behavior in low power FERAM device. Nano Energy 34, 103–110 (2017). Retrieved from https://www.sciencedirect.com/science/article/pii/S2211285517300794, https://doi.org/10.1016/j.nanoen.2017.02.008

  18. Cho, S., Lee, H.: Flip-n-write: a simple deterministic technique to improve pram write performance, energy and endurance. In: 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (Micro), pp. 347–357 (2009).

    Google Scholar 

  19. Daulby, T., Savanth, A., Weddell, A.S., Merrett, G.V.: Comparing NVM technologies through the lens of intermittent computation. In: Proceedings of the 8th International Workshop on Energy Harvesting and Energy-Neutral Sensing Systems, pp. 77–78. Association for Computing Machinery, New York (2020). Retrieved from https://doi.org/10.1145/3417308.3430268

  20. Ding, K., Chen, B., Chen, Y., Wang, J., Shen, X., Rao, F.: Recipe for ultrafast and persistent phase-change memory materials. NPG Asia Mater. 12(1), 63 (2020, September 25). Retrieved from https://doi.org/10.1038/s41427-020-00246-z

  21. Dong, X., Xu, C., Xie, Y., Jouppi, N.P.: NVSIM: a circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comp-Aid. Des. Integr. Circuits Syst. 31(7), 994–1007 (2012). https://doi.org/10.1109/TCAD.2012.2185930

    Article  Google Scholar 

  22. Fey, D., Reuben, J., Slesazeck, S.: Comparative study of usefulness of FEFET, FTJ and RERAM technology for ternary arithmetic. In: 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 1–6 (2021). https://doi.org/10.1109/ICECS53924.2021.9665635

  23. Fong, S.W., Neumann, C.M., Wong, H.-S.P.: Phase-change memory—towards a storage-class memory. IEEE Trans. Electron Devices. 64(11), 4374–4385 (2017). https://doi.org/10.1109/TED.2017.2746342

    Article  Google Scholar 

  24. Gamatié, A., Nocua, A., Weloli, J.W., Sassatelli, G., Torres, L., Novo, D., Robert, M.: Emerging NVM Technologies in Main Memory for Energy-Efficient HPC: an Empirical Study (2019, May). Retrieved from https://hal-lirmm.ccsd.cnrs.fr/lirmm-02135043 (working paper or preprint)

  25. Gilmer, D.C., Rueckes, T., Cleveland, L., Viviani, D.: Nram status and prospects. In: 2017 IEEE International Conference on IC Design and Technology (ICICDT), pp. 1–4 (2017, May). https://doi.org/10.1109/ICICDT.2017.7993504

  26. Gilmer, D. C., Rueckes, T., Cleveland, L.: NRAM: a disruptive carbon-nanotube resistance-change memory. Nanotechnology 29(13), 134003 (2018, February). Retrieved from https://doi.org/10.1088/1361-6528/aaaacb

  27. Gong, N.: Multi level cell (MLC) in 3D crosspoint phase change memory array. Sci. China Inf. Sci. 64, 166401 (2021). https://doi.org/10.1007/s11432-021-3184-5

    Article  Google Scholar 

  28. Hu, M., Li, H., Wu, Q., Rose, G. S.: Hardware realization of BSB recall function using memristor crossbar arrays. In: Proceedings of the 49th Annual Design Automation Conference, pp. 498–503. ACM, New York (2012). Retrieved from https://doi.org/10.1145/2228360.2228448

  29. Hu, D., Lv, F., Wang, C., Cui, H.-M., Wang, L., Liu, Y., Feng, X.-B.: NVM streaker: a fast and reconfigurable performance simulator for non-volatile memory-based memory architecture. J. Supercomput. 74(8), 3875–3903 (2018, August 01). Retrieved from https://doi.org/10.1007/s11227-018-2438-y

  30. Iuga, A., Lindfors-Vrejoiu, I., Boni, G.: Ultrafast nondestructive pyroelectric reading of feram memories. Infr. Phys. Technol. 116, 103766 (2021). Retrieved from https://www.sciencedirect.com/science/article/pii/S1350449521001389, https://doi.org/10.1016/j.infrared.2021.103766

  31. Jin, H., Chen, D., Liu, H., Liao, X., Guo, R., Zhang, Y.: Miss penalty aware cache replacement for hybrid memory systems. IEEE Trans. Comp-Aid. Des. Integr. Circuits Syst. 39(12), 4669–4682 (2020). https://doi.org/10.1109/TCAD.2020.2966482

    Article  Google Scholar 

  32. Kallinatha, H.D., Talawar, B.: Comparative analysis of non-volatile memory on-chip caches (2022)

    Google Scholar 

  33. Kamath, A.K., Monis, L., Karthik, A.T., Talawar, B.: Storage class memory: principles, problems, and possibilities. arXiv (2019). Retrieved from https://arxiv.org/abs/1909.12221, https://doi.org/10.48550/ARXIV.1909.12221

  34. Kariyappa, S., Tsai, H., Spoon, K., Ambrogio, S., Narayanan, P., Mackin, C., et al.: Noise-resilient DNN: tolerating noise in PCM-based AI accelerators via noise-aware training. IEEE Trans. Electron Devices. 68(9), 4356–4362 (2021). https://doi.org/10.1109/TED.2021.3089987

    Article  Google Scholar 

  35. Kim, T., Lee, S.: Evolution of phase-change memory for the storage class memory and beyond. IEEE Trans. Electron Devices. 67(4), 1394–1406 (2020). https://doi.org/10.1109/TED.2020.2964640

    Article  Google Scholar 

  36. Kim, Y., Zhang, Y., Li, P.: A reconfigurable digital neuromorphic processor with memristive synaptic crossbar for cognitive computing. J. Emerg. Technol. Comput. Syst. 11(4), 38:1–38 (2015, April). Retrieved from http://doi.acm.org/10.1145/2700234

  37. Kim, S., Sun, J., Choi, Y., Lim, D.U., Kang, J., Cho, J.H.: Carbon nanotube ferroelectric random access memory cell based on omega-shaped ferroelectric gate. Carbon 162, 195–200 (2020). Retrieved from https://www.sciencedirect.com/science/article/pii/S0008622320301901, https://doi.org/10.1016/j.carbon.2020.02.044

  38. Kokolis, A., Skarlatos, D., Torrellas, J.: PageSeer: using page walks to trigger page swaps in hybrid memory systems. In: 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 596–608 (2019)

    Google Scholar 

  39. Li, B., Shan, Y., Hu, M., Wang, Y., Chen, Y., Yang, H.: Memristor-based approximated computation. In: Proceedings of the 2013 International Symposium on Low Power Electronics and Design, pp. 242–247. IEEE Press, Piscataway (2013). Retrieved from http://dl.acm.org/citation.cfm?id=2648668.2648729

  40. Liang, Y.-P., Chen, S.-H., Chang, Y.-H., Liu, Y.-F., Wei, H.-W., Shih, W.-K.: A cache consolidation design of MLC STT-ram for energy efficiency enhancement on cyber-physical systems. SIGAPP Appl. Comput. Rev. 21(1), 37–49 (2021). Retrieved from https://doi.org/10.1145/3477133.3477136

  41. Liu, Y., Li, H., Lu, Y., Chen, Z., Xiao, N., Zhao, M.: HASFS: optimizing file system consistency mechanism on NVM-based hybrid storage architecture. Clust. Comput. 23(4), 2501–2515 (2020, December 01). Retrieved from https://doi.org/10.1007/s10586-019-03023-y

  42. Luo, J.-Y., Cheng, H.-Y., Lin, I.-C., Chang, D.-W.: Tap: reducing the energy of asymmetric hybrid last-level cache via thrashing aware placement and migration. IEEE Trans. Comput. 68(12), 1704–1719 (2019). https://doi.org/10.1109/TC.2019.2917208

    Article  MATH  Google Scholar 

  43. Mao, H., Zhang, X., Sun, G., Shu, J.: Protect nonvolatile memory from wear-out attack based on timing difference of row buffer hit/miss. In: Design, Automation Test in Europe Conference Exhibition (DATE), 2017, pp. 1623–1626 (2017, March). https://doi.org/10.23919/DATE.2017.7927251

  44. Meena, J.S., Sze, S.M., Chand, U., Tseng, T.-Y.: Overview of emerging nonvolatile memory technologies. Nanoscale Res. Lett. 9(1), 526 (2014, September 25). Retrieved from https://doi.org/10.1186/1556-276X-9-526

  45. Mittal, S.: A survey of ReRam-based architectures for processing in-memory and neural networks. Mach. Learn. Knowl. Extr. 1(1), 75–114 (2018). Retrieved from http://www.mdpi.com/2504-4990/1/1/5, https://doi.org/10.3390/make1010005

  46. Mittal, S., Vetter, J.S.: A survey of software techniques for using non-volatile memories for storage and main memory systems. IEEE Trans. Parallel Distrib. Syst. 27(5), 1537–1550 (2016). https://doi.org/10.1109/TPDS.2015.2442980

    Article  Google Scholar 

  47. Ni, M., Chen, L., Hao, X., Sun, H., Liu, C., Zhang, Z., … Pan, L.: A novel prefetching scheme for non-volatile cache in the AIOT processor. In: 2020 5th International Conference on Universal Village (UV), pp. 1–7 (2020). https://doi.org/10.1109/UV50937.2020.9426214

  48. Palangappa, P.M., Mohanram, K.: Flip-mirror-rotate: an architecture for bit-write reduction and wear leveling in non-volatile memories. In: Proceedings of the 25th Edition on Great Lakes Symposium on VLSI, pp. 221–224. Association for Computing Machinery, New York (2015). Retrieved from https://doi.org/10.1145/2742060.2742110

  49. Poremba, M., Xie, Y.: NV Main: an architectural-level main memory simulator for emerging non-volatile memories. In: 2012 IEEE Computer Society Annual Symposium on VLSI, pp. 392–397 (2012). https://doi.org/10.1109/ISVLSI.2012.82

  50. Poremba, M., Mittal, S., Li, D., Vetter, J.S., Xie, Y.: Destiny: a tool for modeling emerging 3D NVM and EDRAM caches. In: 2015 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1543–1546 (2015). https://doi.org/10.7873/DATE.2015.0733

  51. Prezioso, M., Merrikh-Bayat, F., Hoskins, B.D., Adam, G.C., Likharev, K.K., Strukov, D.B.: Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521(61) (2015). Retrieved from https://doi.org/10.1038/nature14441

  52. Qureshi, M.K., Srinivasan, V., Rivers, J.A.: Scalable high performance main memory system using phase-change memory technology. SIGARCH Comput. Archit. News 37(3), 24–33 (2009, June). Retrieved from https://doi.org/10.1145/1555815.1555760

  53. Rashidi, S., Jalili, M., Sarbazi-Azad, H.: A survey on PCM lifetime enhancement schemes. ACM Comput. Surv. 52(4) (2019, August). Retrieved from https://doi.org/10.1145/3332257

  54. Rosendale, G., Viviani, D., Manning, M., Henry Huang, X.M., Rueckes, T., Wen, S.J., Wong, R.: Storage element scaling impact on CNT memory retention and on/off window. In: 2014 IEEE 6th International Memory Workshop (IMW), pp. 1–3 (2014, May). https://doi.org/10.1109/IMW.2014.6849391

  55. Ryoo, J.H., John, L.K., Basu, A.: A case for granularity aware page migration. In: Proceedings of the 2018 International Conference on Supercomputing, pp. 352–362 (2018). Association for Computing Machinery, New York. Retrieved from https://doi.org/10.1145/3205289.3208064

  56. Samavatian, M.H., Arjomand, M., Bashizade, R., Sarbazi-Azad, H.: Architecting the last-level cache for Gpus using STT-ram technology. ACM Trans. Des. Autom. Electron. Syst. 20(4) (2015, September). Retrieved from https://doi.org/10.1145/2764905

  57. Sebastian, A., Boybat, I., Dazzi, M., Giannopoulos, I., Jonnalagadda, V., Joshi, V., … Eleftheriou, E.: Computational memory-based inference and training of deep neural networks. In: 2019 Symposium on VLSI Technology, pp. T168–T169 (2019). https://doi.org/10.23919/VLSIT.2019.8776518

  58. Sehgal, P., Basu, S., Srinivasan, K., Voruganti, K.: An empirical study of file systems on NVM. In: 2015 31st Symposium on Mass Storage Systems and Technologies (MSST), pp. 1–14 (2015). https://doi.org/10.1109/MSST.2015.7208283

  59. Shafiee, A., Nag, A., Muralimanohar, N., Balasubramonian, R., Strachan, J.P., Hu, M., … Srikumar, V.: Isaac: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. In: Proceedings of the 43rd International Symposium on Computer Architecture, pp. 14–26 (2016). IEEE Press, Piscataway. Retrieved from https://doi.org/10.1109/ISCA.2016.12

  60. Sivakumar, S., Abdul Khader, T., Jose, J.: Improving lifetime of non-volatile memory caches by logical partitioning. In Proceedings of the 2021 on Great Lakes Symposium on VLSI, pp. 123–128 (2021). Association for Computing Machinery, New York. Retrieved from https://doi.org/10.1145/3453688.3461488

  61. Song, L., Qian, X., Li, H., Chen, Y.: Pipelayer: a pipelined reram-based accelerator for deep learning. In: 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 541–552 (2017, February). https://doi.org/10.1109/HPCA.2017.55

  62. Song, L., Zhuo, Y., Qian, X., Li, H., Chen, Y.: Graphr: accelerating graph processing using ReRam. In: 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 531–543 (2018, February). https://doi.org/10.1109/HPCA.2018.00052

  63. Spoon, K., Ambrogio, S., Narayanan, P., Tsai, H., Mackin, C., Chen, A., … Burr, G.W.: Accelerating deep neural networks with analog memory devices. In: 2020 IEEE International Memory Workshop (IMW), pp. 1–4 (2020). https://doi.org/10.1109/IMW48823.2020.9108149

  64. Sun, G., Zhao, J., Poremba, M., Xu, C., Xie, Y.: Memory that never forgets: emerging nonvolatile memory and the implication for architecture design. Natl. Sci. Rev. 5(4), 577–592 (2017, August). Retrieved from https://doi.org/10.1093/nsr/nwx082

  65. Sun, H., Chen, L., Hao, X., Liu, C., Ni, M.: An energy-efficient and fast scheme for hybrid storage class memory in an AIoT terminal system. Electronics 9(6) (2020). Retrieved from https://www.mdpi.com/2079-9292/9/6/1013, https://doi.org/10.3390/electronics9061013

  66. Swami, S., Mohanram, K.: Reliable nonvolatile memories: techniques and measures. IEEE Design Test. 34(3), 31–41 (2017). https://doi.org/10.1109/MDAT.2017.2682252

    Article  Google Scholar 

  67. Swami, S., Palangappa, P.M., Mohanram, K.: ECS: error-correcting strings for lifetime improvements in nonvolatile memories. ACM Trans. Archit. Code Optim. 14(4) (2017, December). Retrieved from https://doi.org/10.1145/3151083

  68. Vetter, J.S., Mittal, S.: Opportunities for nonvolatile memory systems in extreme-scale high-performance computing. Comput. Sci. Eng. 17(2), 73–82 (2015). https://doi.org/10.1109/MCSE.2015.4

    Article  Google Scholar 

  69. Vincent, A.F., Larroque, J., Zhao, W.S., Romdhane, N.B., Bichler, O., Gamrat, C., … Querlioz, D.: Spin-transfer torque magnetic memory as a stochastic Memristive synapse. In: 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1074–1077 (2014, June). https://doi.org/10.1109/ISCAS.2014.6865325

  70. Vincent, A.F., Larroque, J., Locatelli, N., Ben Romdhane, N., Bichler, O., Gamrat, C., et al.: Spin-transfer torque magnetic memory as a stochastic memristive synapse for neuromorphic systems. IEEE Trans. Biomed. Circ. Syst. 9(2), 166–174 (2015, April). https://doi.org/10.1109/TBCAS.2015.2414423

    Article  Google Scholar 

  71. Walden, C., Singh, D., Jagasivamani, M., Li, S., Kang, L., Asnaashari, M., … Yeung, D.: Monolithically integrating non-volatile main memory over the last-level cache. ACM Trans. Archit. Code Optim. 18(4) (2021, July). Retrieved from https://doi.org/10.1145/3462632

  72. Wang, Z., Liu, X., Yang, J., Michailidis, T., Swanson, S., Zhao, J.: Characterizing and modeling non-volatile memory systems. In: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (Micro), pp. 496–508 (2020). https://doi.org/10.1109/MICRO50266.2020.00049

  73. Xie, M., Li, S., Glova, A.O., Hu, J., Wang, Y., Xie, Y.: Aim: fast and energy-efficient AES in-memory implementation for emerging nonvolatile main memory. In: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 625–628 (2018, March). https://doi.org/10.23919/DATE.2018.8342085

  74. Xu, C., Niu, D., Muralimanohar, N., Jouppi, N.P., Xie, Y.: Understanding the trade-offs in multi-level cell ReRam memory design. In: 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–6 (2013)

    Google Scholar 

  75. Xu, J., Feng, D., Hua, Y., Huang, F., Zhou, W., Tong, W., Liu, J.: An efficient spare-line replacement scheme to enhance nvm security. In: 2019 56th ACM/IEEE Design Automation Conference (DAC), pp. 1–6 (2019)

    Google Scholar 

  76. Xue, C.J., Sun, G., Zhang, Y., Yang, J.J., Chen, Y., Li, H.: Emerging non-volatile memories: opportunities and challenges. In: 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (Codes+ISSS), pp. 325–334 (2011). https://doi.org/10.1145/2039370.2039420

  77. Zahoor, F., Azni Zulkifli, T.Z., Khanday, F.A.: Resistive random access memory (RRAM): an overview of materials, switching mechanism, performance, multilevel cell (MLC) storage, modeling, and applications. Nanoscale Res. Lett. 15(1), 90 (2020, April 22). Retrieved from https://doi.org/10.1186/s11671-020-03299-9

  78. Zhang, Y., Zhang, L., Wen, W., Sun, G., Chen, Y.: Multi-level cell STT-ram: is it realistic or just a dream? In: 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 526–532 (2012)

    Google Scholar 

  79. Zhang, M., Zhang, L., Jiang, L., Liu, Z., & Chong, F.T. Balancing performance and lifetime of MLC PCM by using a region retention monitor. In: 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 385–396 (2017a). https://doi.org/10.1109/HPCA.2017.45

  80. Zhang, Z., Fu, Y., Hu, G.: Dualstack: a high efficient dynamic page scheduling scheme in hybrid main memory. In: 2017 International Conference on Networking, Architecture, and Storage (NAS), pp. 1–6 (2017b)

    Google Scholar 

  81. Zhang, M., Zhang, L., Jiang, L., Chong, F.T., Liu, Z.: Quickand-dirty: an architecture for high-performance temporary short writes in MLC PCM. IEEE Trans. Comput. 68(9), 1365–1375 (2019). https://doi.org/10.1109/TC.2019.2900036

    Article  MathSciNet  MATH  Google Scholar 

  82. Zhao, W., Tong, W., Feng, D., Liu, J., Xu, J., Wei, X., … Liu, B.: OSwrite: improving the lifetime of MLC STT-ram with one-step write (2020)

    Google Scholar 

  83. Zhu, G., Han, J., Lee, S., Son, Y.: An empirical evaluation of NVM-aware file systems on intel Optane DC persistent memory modules. In: 2021 International Conference on Information Networking (ICOIN), pp. 559–564 (2021). https://doi.org/10.1109/ICOIN50884.2021.9333911

Download references

Author information

Authors and Affiliations

  1. SPARK Lab, Department of Computer Science and Engineering, National Institute of Technology Karnataka (NITK), Surathkal, India

    Sadhana Rai & Basavaraj Talawar

Authors
  1. Sadhana Rai
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Basavaraj Talawar
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sadhana Rai .

Editor information

Editors and Affiliations

  1. Silicon Valley Polytechnic Institute, Los Altos Hills, CA, USA

    Ali Iranmanesh

Rights and permissions

Reprints and permissions

Copyright information

© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Rai, S., Talawar, B. (2023). Nonvolatile Memory Technologies: Characteristics, Deployment, and Research Challenges. In: Iranmanesh, A. (eds) Frontiers of Quality Electronic Design (QED). Springer, Cham. https://doi.org/10.1007/978-3-031-16344-9_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-031-16344-9_4

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-16343-2

  • Online ISBN: 978-3-031-16344-9

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation