Skip to main content

Introduction

  • Chapter
  • First Online:
Technology Mapping for LUT-Based FPGA

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 713))

Abstract

The design process of digital systems requires the use of specialized computer-aided design (CAD) software. The diversity of digital circuit implementations and the domination of application-specific integrated circuits (ASICs) create many problems in the field of automatic synthesis. Describing the designed systems and converting description to a form implemented in hardware are challenging. These problems have contributed to the development of high-level forms of system description, which may include hardware description languages or even system description languages.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. www.altera.com

  2. www.xilinx.com

  3. www.actel.com

  4. Czerwiński R, Kania D (2009) Synthesis of finite state machines for CPLDs. Int J Appl Math Comput Sci (AMCS) 19(4):647–659

    Article  MATH  Google Scholar 

  5. Czerwiński R, Kania D (2010) A synthesis of high speed finite state machines. Bull Polish Acad Sci Tech Sci 58(4):635–644

    Google Scholar 

  6. Kania D (2007) A new approach to logic synthesis of multi-output boolean functions on PAL-based CPLDs. In: Proceedings of the ACM great lakes symposium on VLSI, GLSVLSI’07 Stressa - Lago Maggiore, Italy, March, 11–13, 2007, pp 152–155

    Google Scholar 

  7. Kania D, Kubica M (2015) Technology mapping based on modified graph of outputs. In: International conference of computational methods in sciences and engineering, AIP Conference Proceedings, vol 1702

    Google Scholar 

  8. Opara A, Kania D (2010) Decomposition-based logic synthesis for PAL-based CPLDs. Int J Appl Math Comput Sci 20(2):367–384

    Article  MATH  Google Scholar 

  9. Opara A, Kania D (2015) Logic synthesis strategy based on BDD decomposition and PAL-oriented optimization. In: 11th international conference of computational methods in sciences and engineering, ICCMSE 2015, 20–23 March 2015, Athens, Greece, AIP Conf. Proc. 1702, 2015, 060002-1–4

    Google Scholar 

  10. Opara A, Kubica M (2016) Decomposition synthesis strategy directed to FPGA with special MTBDD representation. In: International conference of computational methods in sciences and engineering, American Institute of Physics, Athens, 17 Mar 2016, AIP conference proceedings, vol 1790

    Google Scholar 

  11. Cong J, Minkovich K (2007) Optimality study of logic synthesis for LUT-based FPGAs. IEEE Trans CAD 2(2):230–239

    Article  Google Scholar 

  12. Kania D (2011) Efficient technology mapping method for PAL-based devices, design of digital systems and devices, book series. Lecture Notes in Electrical Engineering 79:145–163

    Article  MATH  Google Scholar 

  13. Kania D (2015) Logic decomposition for PAL-based CPLDs. J Circuits Syst Comput 24(3):1–27

    Article  MathSciNet  Google Scholar 

  14. Opara A, Kubica M, Kania D (2019) Methods of improving time efficiency of decomposition dedicated at FPGA structures and using BDD in the process of cyber-physical synthesis. IEEE Access 7:20619–20631

    Article  Google Scholar 

  15. Bolton M (1990) Digital systems design with programmable logic. Addison-Wesley Publishing Company, Boston

    Google Scholar 

  16. Chen SL, Hwang TT, Liu CL (2002) A technology mapping algorithm for CPLD architectures. In: IEEE international conference on field-programmable technology, Hong Kong, December 16–18, 2002, pp. 204–210

    Google Scholar 

  17. Czerwiński R, Kania D (2013) Finite state machine logic synthesis for CPLDs, Springer, Lecture Notes in Electrical Engineering, vol 231, XVI, 172 p

    Google Scholar 

  18. Kania D (2000) A technology mapping algorithm for PAL-based devices using multi-output function graphs. In: Proceedings of 26-th Euromicro Conference, IEEE Computer Society Press, Maastricht, 2000, pp 146–153

    Google Scholar 

  19. Kania D (2002) Logic synthesis of multi-output functions for PAL-based CPLDs. In: IEEE international conference on field-programmable technology, Hong Kong, December 16–18, pp 429–432

    Google Scholar 

  20. Kania D, Kulisz J, Milik A (2005) A novel method of two-stage decomposition dedicated for PAL-based CPLDs. In: Proceedings of Euromicro symposium on digital system design, IEEE Computer Society Press, Porto, September, pp 114–121

    Google Scholar 

  21. Espresso (1993) A source code. http://embedded.eecs.berkeley.edu/pubs/downloads/espresso/index.htm

  22. Murgai R, Nishizaki Y, Shenay N, Brayton RK, Sangiovanni-Vincentelli A (1990) Logic synthesis for programmable gate array. In: Proceedings of 27th DAC, June 1990, pp 620–625

    Google Scholar 

  23. Murgai R, Shenoy N, Brayton RK, Sangiovanni-Vincentelli A (1991) Improved logic synthesis algorithms for table look up architectures. ICCAD-91, Santa Clara, CA, pp 564–567

    Google Scholar 

  24. Abouzeid P, Babba B, Crastes M, Saucier G (1993) Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs. IEEE Trans on CAD 12(7):913–925

    Article  Google Scholar 

  25. Ashenhurst RL (1957) The decomposition of switching functions. In: Proceedings of an international symposium on the theory of switching, April 1957

    Google Scholar 

  26. Brown SD, Francis RJ, Rose J, Vranesic ZG (1993) Field programmable gate arrays. Kluwer Academic Publishers, Boston, pp 45–86

    Google Scholar 

  27. Brayton RK, Hachtel GD, McMullen C, Sangiovanni-Vincentelli AL (1984) Logic minimization algorithms for VLSI synthesis. Kluwer Academic Publishers, Boston

    Google Scholar 

  28. Brayton RK, Hachtel GD, Sangiovanni-Vincentelli AL (1990) Multilevel logic synthesis. Proc IEEE 78(2):264–300

    Article  Google Scholar 

  29. Cong J, Ding Y (1994) FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA design. IEEE Trans Comput-Aided Des 13(1):1–12

    Article  Google Scholar 

  30. De Micheli G (1994) Synthesis and optimization of digital circuits. McGraw-Hill, Inc.

    Google Scholar 

  31. Chen D, Cong J (2004) DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. Computer Aided Design, 2004. IEEE/ACM International Conference on ICCAD-2004, pp 752–759

    Google Scholar 

  32. Gowda T, Vrudhula S, Kulkarni N, and Berezowski K (2011) Identification of threshold functions and synthesis of threshold networks. IEEE Trans Comput-Aided Des Integr Circuits Syst 30(5)

    Google Scholar 

  33. Pistorius J, Hutton M, Mishchenko A, Brayton R (2007) Benchmarking method and designs targeting logic synthesis for FPGAs. In: Proceedings of Int’l workshop on logic and synthesis, vol 7

    Google Scholar 

  34. Curtis HA (1962) The design of switching circuits. D. van Nostrand Company Inc, Princeton

    Google Scholar 

  35. Curtis HA (1963) Generalized tree circuit—the basic building block of an extended decomposition theory. J ACM 10:562–581

    Google Scholar 

  36. Babba B, Crastes M, Saucier G (1992) Input driven synthesis on PLDs and PGAs. In: The European conference on design automation, Brussels (Belgium), March 1992

    Google Scholar 

  37. Huang J-D, Jou J-Y, Shen W-Z (2000) ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans Very Large Integration (VLSI) Syst 8(4):392–400

    Google Scholar 

  38. Legl Ch, Wurth B, Eckl K (1995) An implicit algorithm for support minimization during functional decomposition. ED&TC, Paris, pp 412–417

    Google Scholar 

  39. Pan KR, Pedram M (1996) FPGA synthesis for minimum area, delay and power, ED&TC, Paris, p 603

    Google Scholar 

  40. Wan W, Perkowski MA (1992) A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its applications to FPGA mapping. Proceedings of EDAC’92, pp 230–235

    Google Scholar 

  41. Kania D (2000) Decomposition-based synthesis and its application in PAL-oriented technology mapping. In: Proceedings of 26-th Euromicro conference, IEEE Computer Society Press, Maastricht, pp 138–145

    Google Scholar 

  42. Kubica M, Kania D (2016) SMTBDD: new form of BDD for logic synthesis. Int J Electron Telecommun 62(1):33–41

    Google Scholar 

  43. Perkowski M, Malvi R, Grygiel S, Burns M, Mishchenko A (1999) Graph coloring algorithms for fast evaluation of Curtis decompositions, 36-th ACM/IEEE DAC’99, New Orleans

    Google Scholar 

  44. Selveraj H, Łuba T, Nowicka M, Bignall B. Multiple-valued decomposition and its applications in data compression and technology mapping, ICCIMA’97

    Google Scholar 

  45. Jozwiak L, Chojnacki A (2003) Effective and efficient FPGA synthesis through general functional decomposition. J. Syst Archit 49(4–6):247–265. ISSN 1383-7621

    Google Scholar 

  46. Kania D, Kulisz J (2007) Logic synthesis for PAL-based CPLD-s based on two-stage decomposition. J Syst Softw 80:1129–1141

    Article  Google Scholar 

  47. Kania D, Milik A (2010) Logic Synthesis based on decomposition for CPLDs. Microprocess Microsyst 34:25–38

    Article  Google Scholar 

  48. Chang S, Marek-Sadowska M, Hwang T (1996) Technology mapping for TLU FPGA’s based on decomposition of binary decision diagrams. IEEE Trans. Comput-Aided Des 15(10):1226–1235

    Article  Google Scholar 

  49. Ebend R, Fey G, Drechsler R (2005) Advanced BDD optimization. Springer, Dordrecht

    Google Scholar 

  50. Kubica M, Opara A, Kania D (2017) Logic synthesis for FPGAs based on cutting of BDD. Microprocess Microsyst 52:173–187

    Article  Google Scholar 

  51. Lai Y, Pedram M, Vrudhula S (1994) EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. IEEE Trans Comput Aided Des 13(8):959–975

    Article  Google Scholar 

  52. Lai Y, Pan KR, Pedram M (1996) OBDD-based function decomposition: algorithms and implementation. IEEE Trans Comput-Aided Des 15(8):977–990

    Article  Google Scholar 

  53. Machado L, Cortadella J, Support-reducing decomposition for FPGA mapping. IEEE Trans Comput-Aided Des Integr Circuits Syst 39(1):213–224

    Google Scholar 

  54. Opara A, Kubica M (2017) Optimization of synthesis process directed at FPGA circuits with the usage of non-disjoint decomposition. In: Proceedings of the international conference of computational methods in sciences and engineering 2017, American Institute of Physics, Thessaloniki, 21 Apr 2017, Seria: AIP Conference Proceedings, vol 1906, Art. no. 120004

    Google Scholar 

  55. Opara A, Kubica M, Kania D (2018) Strategy of logic synthesis using MTBDD dedicated to FPGA. Integr VLSI J 62:142–158

    Article  Google Scholar 

  56. Opara A, Kubica M (2018) The choice of decomposition taking non-disjoint decomposition into account. In: Proceedings of the international conference of computational methods in sciences and engineering 2018, American Institute of Physics, Thessaloniki, 14 Mar 2018, AIP Conference Proceedings, vol 2040, Art. no. 080010

    Google Scholar 

  57. Sasao T (1993) FPGA design by generalized functional decomposition in logic synthesis and optimization. Kluwer Academic Publishers, Boston

    Book  Google Scholar 

  58. Scholl A (2001) Functional decomposition with application to FPGA synthesis. Kluwer Academic Publishers, Boston

    Book  MATH  Google Scholar 

  59. Zhang H, Chen Z, Wang P (2019) Area and delay optimization of binary decision diagrams mapped circuit. J Electr Inf Technol 41(3):725–731

    Google Scholar 

  60. Yang C, Ciesielski M (2002) BDS: a BDD-based logic optimization system. IEEE Trans Comput-Aided Des Integ Circuits Syst 21(7):866–876

    Article  Google Scholar 

  61. Vemuri N, Kalla P, Tessier R (2002) A BDD—based logic synthesis for LUT—based FPGAs. ACM Trans Des Autom Electron Devices 7(4):501–525

    Article  Google Scholar 

  62. Cheng L, Chen D, Wong MDF (2007) DDBDD: delay-driven BDD synthesis for FPGAs. In: Design automation conference, 2007, DAC ’07. 44th ACM/IEEE, 2007, pp 910–915

    Google Scholar 

  63. Berkeley Logic Synthesis Group (2005) ABC: a system for sequential synthesis and verification, Dec. 2005. Available: http://www.eecs.berkeley.edu/~alanmi/abc

  64. Fiser P, Schmidt J (2009) The case for a balanced decomposition process. In: Proceedings of 12th Euromicro conference on digital systems design (DSD), Patras (Greece), pp 601–604

    Google Scholar 

  65. Fiser P, Schmidt J (2012) On using permutation of variables to improve the iterative power of resynthesis, in Proc. of 10th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), pp 107–114

    Google Scholar 

  66. Liang YY, Kuo TY, Wang SH, Mak WK (2010) ALMmap: technology mapping for FPGAs with adaptive logic modules, computer-aided design (ICCAD). In: 2010 IEEE/ACM international conference on, pp 143–148

    Google Scholar 

  67. Kubica M, Kania D, Kulisz J (2019) A technology mapping of FSMs based on a graph of excitations and outputs IEEE Access, vol 7, pp 16123–16131

    Google Scholar 

  68. Kubica M, Kania D (2019) Graph of outputs in the process of synthesis directed at CPLDs, Mathematics 7(12):1–17, Art. no. 1171

    Google Scholar 

  69. Kajstura K, Kania D (2011) A decomposition state assignment method of finite state machines oriented towards minimization of Power. Przegląd Elektrotechniczny 87(6):146–150

    Google Scholar 

  70. Kajstura K, Kania D (2016) Binary tree-based low power state assignment algorithm. In: 12-th international conference of computational methods in science and engineering, ICCMSE 2016, 17–20 March 2016, Athens, Greece, AIP Conference Proceedings 1790, 2016, pp 0300007_1–0300007_4

    Google Scholar 

  71. Kajstura K, Kania D (2018) Low power synthesis of finite state machines state assignment decomposition algorithm. J Circuits Syst Comput 27(3):1850041-1–1850041-14

    Google Scholar 

  72. Kubica M, Kajstura K, Kania D (2018) Logic synthesis of low power FSM dedicated into LUT-based FPGA. In: Proceedings of the international conference of computational methods in sciences and engineering 2018. American Institute of Physics, Thessaloniki, 14 Mar 2018, AIP Conference Proceedings, vol 2040

    Google Scholar 

  73. Mengibar L, Entrena L, Lorenz MG, Millan ES (2005) Patitioned state encoding for low Power in FPGAs. Electron Lett 41:948

    Article  Google Scholar 

  74. Kobylecki M, Kania D (2017) FPGA implementation of bit controller in double-tick architecture. In: 13-th international conference of computational methods in science and engineering, ICCMSE 2017, 21–25 April 2017, Thessaloniki, Greece, AIP Conference Proceedings 1906, pp 120008_1–120008_4

    Google Scholar 

  75. Milik A, Hrynkiewicz E (2018) Hardware mapping strategies of PLC programs in FPGAs. In: 15th IFAC conference on programmable devices and embedded systems. PDeS 2018, Ostrava, Czech Republic, 23–25 May 2018. Amsterdam, Elsevier, 2018, pp 131–137

    Google Scholar 

  76. Mocha J, Kania D (2012) Hardware implementation of a control program in FPGA structures. Przegląd Elektrotechniczny R.88(12a):95–100

    Google Scholar 

  77. Wyrwoł B (2011) Using graph greedy coloring algorithms in the hardware implementation of the HFIS fuzzy inference system. Przegląd Elektrotechniczny, Warszawa, nr 10, R. 87:64–67

    Google Scholar 

  78. Ziebinski A, Bregulla M, Fojcik M, Klak S (2017) Monitoring and controlling speed for an autonomous mobile platform based on the hall sensor. In: Nguyen NT, Papadopoulos GA, Jędrzejowicz P, Trawiński B, Vossen G (eds) Computational collective intelligence: 9th international conference, ICCCI 2017, Nicosia, Cyprus, 27–29 Sept 2017, Proceedings, Part II. 2017, pp 249–259

    Google Scholar 

  79. Czerwinski R, Rudnicki T (2014) Examination of electromagnetic noises and practical operations of a PMSM motor driven by a DSP and controlled by means of field oriented control. Elektronika Ir Elektrotechnika 20(5):46–50

    Article  Google Scholar 

  80. Pamula D, Ziebinski A (2009) Hardware implementation of the MD5 algorithm. In: Proceedings of programmable devices and embedded systems conference, Roznov pod Radhostem, pp 45–50

    Google Scholar 

  81. Pułka A, Milik A (2012) Hardware implementation of fuzzy default logic. In: Hippe ZS, Kulikowski JL (eds) Human-computer systems interaction backgrounds and applications II, Series: Advances in Intelligent and Soft Computing, vol 99. Springer, Berlin, pp 325–343

    Google Scholar 

  82. Rudnicki T, Czerwinski R, Sikora A, Polok D (2016) Impact of PWM control frequency onto efficiency of a 1 kW Permanent Magnet Synchronous Motor (PMSM). Elektronika Ir Elektrotechnika 22(6):10–16

    Article  Google Scholar 

  83. Pułka A, Milik A (2011) An efficient hardware implementation of smith-waterman algorithm based on the incremental approach. Int J Electron Telecommun 57(4):489–496

    Article  Google Scholar 

  84. Pułka A, Milik A (2012) Measurement aspects of the genome patterns investigations—hardware implementation. Metrol Meas Syst 19(1):49–62

    Google Scholar 

  85. Ziebinski A, Swierc S (2016) Soft core processor generated based on the machine code of the application. J Circuits Syst Comput 25(04):1650029

    Article  Google Scholar 

  86. Wyrwoł B, Hrynkiewicz E (2013) Decomposition of the fuzzy inference system for implementation in the FPGA structure. In: Int J Appl Math Comput Sci 23(2):473–483

    Google Scholar 

  87. Wyrwoł B, Hrynkiewicz E (2016) Implementation of a microcontroller-based simplified FITA-FIS model. Microprocess Microsyst 44:22–27

    Article  Google Scholar 

  88. Wyrwoł B (2019) Implementation of the FATI hierarchical fuzzy inference system using the immutability decomposition method. Fuzzy Sets and Systems. Elsevier, Amsterdam, pp 1–19

    Google Scholar 

  89. Grobelna I, Wisniewski R, Grobelny M, Wisniewska M (2017) Design and verification of real-life processes with application of petri nets. IEEE Trans Syst Man Cybern Syst 47(11):2856–2869

    Article  Google Scholar 

  90. Wisniewski R, Bazydlo G, Gomes L, Costa A (2017) Dynamic partial reconfiguration of concurrent control systems implemented in FPGA devices. IEEE Trans Industr Inf 13(4):1734–1741

    Article  Google Scholar 

  91. Wiśniewski R (2017) Prototyping of concurrent control systems implemented in FPGA devices. Springer International Publishing, Berlin

    Book  MATH  Google Scholar 

  92. Wiśniewski R (2018) Dynamic partial reconfiguration of concurrent control systems specified by petri nets and implemented in Xilinx FPGA devices. IEEE Access 6:32376–32391

    Article  Google Scholar 

  93. Sułek W (2016) Non-binary LDPC decoders design for maximizing throughput of an FPGA implementation. Circuits Syst Signal Process 35:4060–4080

    Article  Google Scholar 

  94. Sułek W (2019) Protograph based low-density parity-check codes design with mixed integer linear programming. IEEE Access 7:1424–1438

    Article  Google Scholar 

  95. Cupek R, Piękoś P, Poczobut M, Ziebinski A (2010) FPGA based “intelligent tap” device for real-time ethernet network monitoring, computer networks. Proc Ser: Commun Comput Inf Sci 79:58–66

    Google Scholar 

  96. Chmiel M, Czerwinski R, Smolarek P (2015) IEC 61131-3-based PLC Implemented by means of FPGA. In: 13th IFAC conference on programmable devices and embedded systems, PDeS’15, 13–15 May 2015, pp 383–388

    Google Scholar 

  97. Chmiel M, Kulisz J, Czerwinski R, Krzyzyk A, Rosol M, Smolarek P (2016) An IEC 61131-3-based PLC implemented by means of an FPGA. Microprocess Microsyst 44:28–37

    Article  Google Scholar 

  98. Mazur P, Chmiel M, Czerwinski R (2016) Central processing unit of IEC 61131-3-based PLC. In: 14th IFAC conference on programmable devices and embedded systems, PDeS’16, 5–7 October 2016, pp 111–116

    Google Scholar 

  99. Nawrath R, Czerwiński R (2018) FPGA-based implementation of APB/SPI bridge. In: 14th international conference of computational methods in sciences and engineering, ICCMSE’18, Thessaloniki, Greece, 14–18 March 2018

    Google Scholar 

  100. Milik A (2018) Multiple-core PLC CPU implementation and programming. J Circuits Syst Comput 27(10)

    Google Scholar 

  101. Milik A (2016) On hardware synthesis and implementation of PLC programs in FPGAs. Microprocess Microsyst 44:2–16

    Article  Google Scholar 

  102. Milik A, Pułka A (2011) Automatic implementation of arithmetic operation in reconfigurable logic controllers. In: Proceedings of ECCTD 2011 conference, Linköping, Sweden, Aug 27–30, pp 721–724

    Google Scholar 

  103. Kubica M, Kania D (2015) SMTBDD: new concept of graph for function decomposition. IFAC conference on programmable devices and embedded systems: PDeS

    Google Scholar 

  104. Kubica M, Kania D, Opara A (2016) Decomposition time effectiveness for various synthesis strategies dedicated to FPGA structures. In: 12th international conference of computational methods in science and engineering, ICCMSE 2016, 17–20 March 2016, Athens, Greece, AIP Conference Proceedings

    Google Scholar 

  105. Kubica M, Kania D (2017) Decomposition of multi-output functions oriented to configurability of logic blocks. Bull Polish Acad Sci Tech Sci 65(3):317–331

    Google Scholar 

  106. Kubica M, Kania D (2017) Area-oriented technology mapping for LUT-based logic blocks. Int J Appl Math Comput Sci 27(1):207–222

    Google Scholar 

  107. Kubica M, Milik A, Kania D (2018) Technology mapping of multi-output function into LUT-based FPGA. In: Slanina Z (ed) IFAC conference on programmable devices and embedded systems: PDeS 2018 Ostrava, Czech Republic, 23–25 May 2018. Elsevier, Amsterdam, 2018, pp 107–112

    Google Scholar 

  108. Kubica M, Kania D (2019) Technology mapping oriented to adaptive logic modules. Bull Polish Acad Sci—Tech Sci 67(5):947–956

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2021 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Kubica, M., Opara, A., Kania, D. (2021). Introduction. In: Technology Mapping for LUT-Based FPGA. Lecture Notes in Electrical Engineering, vol 713. Springer, Cham. https://doi.org/10.1007/978-3-030-60488-2_1

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-60488-2_1

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-60487-5

  • Online ISBN: 978-3-030-60488-2

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics