Abstract
Most of the recently proposed hardware realizations for non-binary low-density parity-check decoders are ASIC oriented as they employ multiplierless computation units. In this article, we present a different decoder design approach that is specifically intended for an FPGA implementation. We reformulate the mixed-domain FFT-BP decoding algorithm and develop a decoder architecture that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA, thus making use of all the types of FPGA resources. Then, the throughput limit achievable in a single FPGA by the proposed decoder is significantly increased. We also consider another important optimization of the decoder implementation, mainly an efficient realization of the permutation units and an approximated evaluation of the nonlinear functions of messages. Another motivation is to make the decoder easily scalable for FPGA devices of different sizes. To achieve this goal, the configurable semi-parallel decoder architecture is applied operating for the structured subclass of codes.
Similar content being viewed by others
References
L. Barnault, D. Declercq, Fast decoding algorithm for LDPC over GF(\(2^q\)), in Proc. (IEEE) Information Theory Workshop, pp. 70–73. Paris, France (2003)
A. Bennatan, D. Burshtein, Design and analysis of nonbinary LDPC codes for arbitrary discrete-memoryless channels. IEEE Trans. Inf. Theory 52, 549–583 (2006)
E. Boutillon, L. Conde-Canecia, A.A. Ghouwayel, Design of a GF(64)-LDPC decoder based on the EMS algorithm. IEEE Trans. Circuits Syst. I 60, 2644–2656 (2013)
J. Chen, L. Wang, Y. Li, Performance comparison between non-binary LDPC codes and Reed–Solomon codes over noise burst channels. in Proc. (IEEE) Int. Conf. Commun., Circuits, Syst., pp. 1–4. Hong Kong (2005)
X. Chen, C.L. Wang, High-throughput efficient non-binary LDPC decoder based on the simplified min–sum algorithm. IEEE Trans. Circuits Syst. I 59, 2784–2794 (2012)
G. Dziwoki, M. Kucharczyk, W. Sulek, Transmission over UWB Channels with OFDM System using LDPC Coding. in Proc. Conference on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments, pp. 75021Q. Wilga, Poland (2009)
M.C. Davey, D. MacKay, Low-density parity check codes over GF(q). IEEE Commun. Lett. 2, 165–167 (1998)
D. Declercq, M. Fossorier, Decoding algorithms for nonbinary LDPC codes over GF(q). IEEE Trans. Commun. 55, 633–643 (2007)
X.Y. Hu, E. Eleftheriou, D.M. Arnold, Regular and irregular progressive edge-growth tanner graphs. IEEE Trans. Inf. Theory 51, 386–398 (2005)
J. Huang, S. Zhou, P. Willett, Nonbinary LDPC coding for multicarrier underwater acoustic communication. IEEE J. Sel. Areas Commun. 26, 1684–1696 (2008)
E. Li, D. Declercq, K. Gunnam, Trellis-based extended min–sum algorithm for non-binary LDPC codes and its hardware structure. IEEE Trans. Commun. 61, 2600–2611 (2013)
J. Lin, J. Sha, Z. Wang, L. Li, Efficient decoder design for nonbinary quasicyclic LDPC codes. IEEE Trans. Circuits Syst. I 57, 1071–1082 (2010)
J.Y.L. Low, C.C. Jong, A memory-efficient tables-and-additions method for accurate computation of elementary functions. IEEE Trans. Comput. 62, 858–872 (2013)
S. Olcer, Decoder Architecture for Array-Code-Based LDPC Codes. in Proc. (IEEE) Global Telecommunications Conference, pp. 2046–2050. San Francisco, USA (2003)
M.E. O’Sullivan, Algebraic construction of sparse matrices with large girth. IEEE Trans. Inf. Theory 52(2), 718–727 (2006)
C. Poulliat, M. Fossorier, D. Declercq, Design of regular (2, dc)-ldpc codes over gf(q) using their binary images. IEEE Trans. Commun. 56, 1626–1635 (2008)
V. Savin, Min–Max decoding for non binary LDPC codes. in Proc. (IEEE) International Symposium on Information Theory, pp. 960–964. Toronto, Canada (2008)
M.J. Schulte, J.E. Stine, Approximating elementary functions with symmetric bipartite tables. IEEE Trans. Comput. 48, 842–847 (1999)
H. Song, J.R. Cruz, Reduced-complexity decoding of Q-ary LDPC codes for magnetic recording. IEEE Trans. Magn. 39, 1081–1087 (2003)
C. Spagnol, E.M. Popovici, W.P. Marnane, Hardware implementation of GF(\(2^m\)) LDPC decoders. IEEE Trans. Circuits Syst. I 56, 2609–2620 (2009)
J.E. Stine, N. Naresh, Compressed symmetric tables for accurate function approximation of reciprocals. in Proc. (IEEE) 6th International Symposium on Circuits and Systems, pp. 799–802. Island of Kos, Greece (2006)
A.G.M. Strollo, D. De Caro, N. Petra, Elementary functions hardware implementation using constrained piecewise-polynomial approximations. IEEE Trans. Comput. 60, 418–432 (2011)
W. Sulek, On the overflow problem in finite precision turbo decoding message passing. IEEE Trans. Commun. 60, 1253–1259 (2012)
W. Sulek, M. Kucharczyk, G. Dziwoki, GF(q) LDPC decoder design for FPGA implementation. in Proc. (IEEE) 10th Annual Consumer Communications & Networking Conference (CCNC), pp. 445–450. Las Vegas, USA (2013)
W. Sulek, Message quantization scheme for nonbinary LDPC decoder FPGA implementation. J. Commun. 10, 86–92 (2015)
Y.L. Ueng, C.Y. Leong, C.J. Yang, C.C. Cheng, K.H. Liao, S.W. Chen, An efficient layered decoding architecture for nonbinary QC-LDPC codes. IEEE Trans. Circuits Syst. I 59, 385–398 (2012)
A. Voicila, D. Declercq, F. Verdier, M. Fossorier, P. Urard, Low-complexity decoding for non-binary LDPC codes in high order fields. IEEE Trans. Commun. 58, 1365–1375 (2010)
A. Voicila, D. Declercq, F. Verdier, M. Fossorier, P. Urard, Architecture of a low-complexity non-binary LDPC decoder for high order fields. in Proc. (IEEE) International Symposium on Communications and Information Technologies, pp. 1201–1206. Sydney, Australia (2007)
H. Wymeersch, H. Steendam, M. Moeneclaey, Log-domain Decoding of LDPC Codes over GF(q). in Proc. (IEEE) International Conference on Communications, pp. 772–776. Paris, France (2004)
H. Wymeersch, H. Steendam, M. Moeneclaey, Computational Complexity and Quantization Effects of Decoding Algorithms for Non-binary LDPC Codes. in Proc. (IEEE) International Conference on Acoustics, Speech, and Signal Processing, pp. 669–672. Montreal, Canada (2004)
L. Zeng, L. Lan, Y. Tai, S. Song, S. Lin, K. Abdel-Ghaffar, Constructions of nonbinary quasi-cyclic LDPC codes: a finite field approach. IEEE Trans. Commun. 56, 545–554 (2008)
X. Zhang, F. Cai, Efficient partial-parallel decoder architecture for quasi-cyclic nonbinary LDPC codes. IEEE Trans. Circuits Syst. I 58, 402–414 (2011)
H. Zhong, T. Zhang, Block-LDPC: a practical LDPC coding system design approach. IEEE Trans. Circuits Syst. I 52, 766–775 (2005)
B. Zhou, J. Kang, S. Song, S. Lin, K. Abdel-Ghaffar, M. Xu, Construction of non-binary quasi-cyclic LDPC codes by arrays and array dispersions. IEEE Trans. Commun. 57, 1652–1662 (2009)
Author information
Authors and Affiliations
Corresponding author
Additional information
This work was supported by the Polish National Science Centre under Grant number 4698/B/T02/2011/40 as well as by the Polish Ministry of Science and Higher Education funding for statutory activities.
Rights and permissions
About this article
Cite this article
Sułek, W. Non-binary LDPC Decoders Design for Maximizing Throughput of an FPGA Implementation. Circuits Syst Signal Process 35, 4060–4080 (2016). https://doi.org/10.1007/s00034-015-0235-x
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-015-0235-x