1 Introduction

On-chip power supply or power-ground (P/G) networks provide power to the circuit modules in a chip from external power supplies. Since power grid wires experience the largest current flows on a chip, they are more susceptible to long-term reliability issues and functional failures. These reliability issues and failures typically come from metal electromigration (EM), excessive IR drops, and ΔI (Ldidt) noise along with recently emerging back end of line time-dependent dielectric breakdown (TDDB) [2, 3, 6].

As technology scales into smaller features with increasing current densities, EM-induced reliability deteriorates, the EM lifetime was projected to be reduced by half for each new technology node by ITRS 2015 [19]. As a result, EM still remains one of the top killers of copper based damascene interconnects for technologies in the sub-10 nm realm. This introduces additional challenges for designing robust power supply networks to satisfy the demanding design requirements.

An important step for power supply synthesis in the typical EDA design flow is sizing the wire width of the power grid stripes, after the topology of the power supply network has been determined, so that the minimum amount of chip area will be used while avoiding potential reliability failures due to electromigration and excessive IR drops. Numerous works have been proposed for the power supply network optimization in the past, primarily based on nonlinear or sequence of linear programming (SLP) methods [8,9,10, 13, 26, 27, 31].

To satisfy the EM reliability, all the existing methods use the current density of individual wires as the constraint, which is mainly based on the Black’s EM model. However, this constraint is too conservative for modern power grid networks. Furthermore, all existing power supply optimization methods fail to consider the aging effects. With recent advancements in physics-based EM models and numerical analysis techniques such as three-phase EM model [12, 24, 28, 33], it is possible to provide more accurate time to failure (TTF) estimation for multi-segment interconnects.

In this chapter, we present two new P/G network sizing and optimization techniques, which were first introduced in [35, 36]. We will summarize the key contributions and major computing steps from the P/G optimization technique considering the new physics-based EM models. The chapter is organized as follows: Sect. 2 describes the power grid network and its models. Section 3 presents the fundamentals of EM and the voltage-based EM immortality check method for general multi-segment interconnect wires. Section 4 outlines a physics-based three-phase EM model and a fast EM lifetime estimation method. Section 5 introduces the EM immortality constrained P/G network optimization problem and its programming-based solution. Section 6 presents the EM lifetime constrained P/G optimization method, which deals with the EM-induced aging effect. Section 7 summarizes this chapter.

2 Power Grid Modeling

Practical VLSI interconnects (especially the global networks such as power supply and clock networks) have many multi-segment wires as shown in Fig. 1. A multi-segment interconnect wire consists of continuously connected high-conductivity metal within one layer of metallization.

Fig. 1
figure 1

Example of a multi-segment wire

Figure 2 shows a typical mesh-structured P/G network with multi-layer power grids. The modeling assumptions for later optimization are listed as follows. Firstly, because of the concern with the long-term average effects of the current, we focus on the steady state (DC) problem, which means we are only interested in the resistance of the power grid networks. Secondly, the P/G network is composed of an orthogonal mesh of wires and contains multiple segments/branches, which is the typical P/G structure. Lastly, to simplify the problem, the circuits are modeled with shorted vias, which means the via resistance is ignored and vias will not be sized. Figure 3 shows the equivalent circuit of the power grid network in Fig. 2.

Fig. 2
figure 2

A small portion of a typical power supply network [22]

Fig. 3
figure 3

Equivalent circuit of a small portion of a typical power grid

As a result, the power grid systems are linear and driven by the DC effective currents [17]. For a power grid network with n nodes,

$$\displaystyle \begin{aligned} G \times V=I {} \end{aligned} $$

where G is a n × n conductance matrix; I is the current source vector; V  is the corresponding vector of nodal voltages.

3 Electromigration Fundamentals

3.1 Electromigration Introduction

EM is a physical phenomenon of material migration caused by an electrical field. Wind force, which is produced by current flowing through a conductor, acts in the direction of the current flow and is the primary cause of EM [21]. During the migration process, hydrostatic stress is generated inside the metal wire due to momentum transfer between lattice atoms. Void and hillock formation are caused by conducting electrons at the opposite ends of the wire. The void may lead to early failure or late failure of the wire [1].

Early failure typically happens in a via-to-via structure as shown in Fig. 4a. When the void forms in a via-above line and reaches critical size [16, 34], which equals the via’s diameter, the via will be blocked by the void and thus the connection to the upper layer will also be blocked. This is because the capping layer is fabricated with dielectrics such as Si3N4 which will block the current flow. On the contrary, late failure typically happens in a via-below structure as shown in Fig. 4b. Since the barrier layer is fabricated with Ta whose resistivity is much higher than Cu, when the void reaches critical size, current can still go through the barrier layer. Sometimes early failure can happen in a via-below structure and late failure can happen in a via-above structure. Although the void can grow at these positions, the possibility is very low.

Fig. 4
figure 4

Side-view of void formation: (a) void in a via-above line (early failure mode); (b) void in a via-below line (later failure mode)

When the compressive stress at the anode continues to be built up, hillocks or extrusion may be formed, which will lead to a resistance decrease [30] and can potentially cause short-circuit failure. However, the void nucleation is still the dominant EM failure effect [15].

3.2 Steady State EM-Induced Stress Modeling

Steady state EM-induced stress modeling helps find the immortality information of the interconnect wire quickly as no complex calculations are required. For these kinds of models, stress on the cathode at steady state (σ steady), which is the maximum stress the node experiences, is compared with critical stress (σ crit). If σ steady is lower than σ crit, the wire is considered as immortal. One of the well-known steady state analysis method is Blech product [4], but it is only suitable for a single (i.e., one-segment) wire. Recently, a voltage-based EM immortality analysis method for multi-segment interconnect structures has been proposed [23, 24]. In this method, an EM voltage (V E) is calculated as

$$\displaystyle \begin{aligned} V_E = \frac{1}{2A} \sum_{k \neq g}a_k V_k {} \end{aligned} $$

where V k is the normal nodal voltage (with respect to cathode node cat) at node k, a k is the total area of branches connected to node k, and A is the total area of the wire. With voltage of node i (V i), steady state stress at that node (σ i) can be calculated as σ i = β(V E − V i), where \(\beta = \frac {eZ}{\Omega }\), e is elementary charge, Z is effective charge number, and Ω is the atomic lattice volume. A critical EM voltage V crit,EM is defined by

$$\displaystyle \begin{aligned} V_{crit,EM} = \frac{1}{\beta} (\sigma_{\text{crit}} - \sigma_{\text{init}}) {} \end{aligned} $$

where σ init is the initial stress. In order to check whether the interconnect wire is immortal, we need to check the following condition

$$\displaystyle \begin{aligned} V_{crit, EM} > V_E - V_{i} \end{aligned} $$

Note that V E − V i is proportional to the stress at cathode node (σ cat).

If this condition is met for all the nodes, EM failure will not happen. Since generally the cathode node has the lowest voltage within an interconnect wire, we may just check the cathode node instead of all the nodes, which means

$$\displaystyle \begin{aligned} V_{crit, EM} > V_E - V_{\text{cat}} \end{aligned} $$

where V cat is the voltage at the cathode. Note that inequality (5) can be applied to both power and ground networks.

The method can be illustrated using the following example. Figure 5 shows a 3-terminal wire. In this wire, node 0 is treated as the ground node. Current densities in two segments are j a and j b which may not be the same because they will be determined by the rest of the circuit. The EM voltage become

Fig. 5
figure 5

Interconnect example for EM analysis for straight 3-terminal wire

$$\displaystyle \begin{aligned} V_E = \frac{ a_0 V_0 + a_1 V_1 + a_2 V_2 }{ 2A } = \frac{ a_1 V_1 + a_2 V_2 }{ 2A } \end{aligned} $$


$$\displaystyle \begin{aligned} V_0 &= 0, & a_0 &= l_a w_a, & \sigma_0 &= \beta V_E \\ V_1 &= j_a l_a \rho, & a_1 &= l_a w_a + l_b w_b, & \sigma_1 &= \beta (V_E - V_1) \\ V_2 &= j_b l_b \rho+ j_al_a\rho, & a_2 &= l_b w_b, & \sigma_2 & = \beta (V_E - V_2) \end{aligned} $$
$$\displaystyle \begin{aligned} A=\frac{a_0+a_1+a_2}{2} \end{aligned} $$

We can compare V E and V crit,EM to see if this wire is immortal.

4 Transient EM-Induced Stress Estimation

In general, the failure process of an interconnect is divided into nucleation phase, incubation phase and growth phase. In the nucleation phase, the stress at the cathode keeps increasing. When it reaches critical stress, a void will be nucleated. The time to reach the critical stress is called nucleation time (t nuc). After the nucleation phase, the void starts to grow (t inc) and eventually leads to wire failure after a period of time (t growth). The TTF or lifetime of the wire can be described as

$$\displaystyle \begin{aligned} TTF = t_{\text{life}} =t_{\text{nuc}}+t_{\text{inc}}+t_{\text{growth}} \end{aligned} $$

4.1 Transient EM-Induced Stress Modeling

4.1.1 Nucleation Phase Modeling

It is well-known that the nucleation phase is accurately modeled by Korhonen’s equation [20]

$$\displaystyle \begin{aligned} \dfrac {\partial \sigma \left( x,t\right) } {\partial t}=\dfrac {\partial } {\partial x}\left[ \kappa\left( \dfrac {\partial \sigma \left( x,t\right) } {\partial x}+\Gamma\right)\right] \end{aligned} $$

where \(\kappa =\frac {D_aB \Omega }{k_BT}\), \(D_a=D_0\text{exp}(-\frac {E_a}{k_BT})\), and \(\Gamma =\frac {eZ}{\Omega }\rho _{w}j\). B is effective bulk elasticity modulus, Ω is atomic lattice volume, k B is Boltzmann constant, T is temperature, Z is effective charge number, ρ w is the wire electrical resistivity, x is coordinate along the line, t is time, and j is current density.

Korhonen’s equation describes the stress distribution accurately; this PDE-based model is hard to solve directly using numerical methods and has very low efficiency for tree-based EM assessment. Recently a few numerical methods have been proposed such as finite difference methods [5, 11] and analytical expressions based approaches [7, 32]. In this work, an integral transformation method for straight multi-segment wires [32] is employed. Suppose we have a multi-segment wire, after discretizing Korhonen’s equation, the stress can be expressed as

$$\displaystyle \begin{aligned} \sigma \left( x,t\right) =\sum _{m=1}^{\infty }\dfrac {\psi _{m} \left( x\right) } {N\left( \lambda_{m}\right) }\bar {\sigma }\left( \lambda_{m},t\right) \end{aligned} $$

where the norm of eigenfunctions N(λ m) is

$$\displaystyle \begin{aligned} N(\lambda_m)=\int^L_{\chi=0}[\psi_m(\chi)]^2d\chi \end{aligned} $$

and the transformed solution of stress \(\bar {\sigma }(\lambda _m,t)\) is

$$\displaystyle \begin{aligned} \bar{\sigma}(\lambda_m,t)=&\left(\int_{\chi=0}^L\psi_m(\chi)\cdot\sigma_0(\chi)d\chi\right)e^{-\kappa\lambda^2_m t}+\frac{1}{\lambda^2_m}\Big(1-e^{\kappa\lambda^2_mt}\Big)\\ &\cdot\sum^n_{k=1}\frac{eZ\rho}{\Omega}j_k \cdot\left(\text{cos}\frac{x_{k-1}}{L}m\pi-\text{cos}\frac{x_k}{L}m\pi\right) \end{aligned} $$

Eigenvalues λ m and eigenfunctions ψ(x) are the solutions of the Sturm–Liouville problem corresponding to the diffusion Eq. (10) and the boundary conditions, which are

$$\displaystyle \begin{aligned} \lambda_m=\frac{m\pi}{L}\text{,}\ \ \psi_m(x)=\text{cos}\frac{x}{L}m\pi \end{aligned} $$

With Eq. (11), given critical stress σ crit, the nucleation time t nuc can be obtained quickly by using nonlinear equation solving methods such as Newton’s method or bisection method.

4.1.2 Incubation Phase Modeling

After the void is nucleated, the incubation phase starts. In this phase, resistance of the interconnect remains almost unchanged since the cross section of the via is not covered by the void and the current can still flow through the copper.

In power grid networks, the interconnect trees are generally multi-segment wires. All segments connected with the void can contribute to the void growth since electron wind at each segment can accelerate or slow down the void growth according to their directions. In this phase, void growth rate v d is estimated to be [25]

$$\displaystyle \begin{aligned} v_{d}=\frac{D_a eZ\rho}{kT W_m }\sum_{i} j_iW_i {} \end{aligned} $$

where j i and W i are the current density and width of the ith segment, respectively. W m is the width of the main segment where the void is formed.

Then the incubation time t inc can be expressed as

$$\displaystyle \begin{aligned} t_{\text{inc}}=\frac{\Delta L_{\text{crit}}}{v_d} {} \end{aligned} $$

where ΔL crit is the critical void length.

4.1.3 Growth Phase Modeling

After the incubation phase, the void fully covers the via, initiating the growth phase. In this phase the resistance starts increasing. It is important to note that, early failure and late failure have different failure mechanisms.

For early failure, the wire fails once the void covers the via, which means the wire fails at the end of incubation phase and there is no growth phase (t growth = 0). Hence the failure time is the sum of t nuc and t inc.

For late failure, after the void size reaches the critical size, there will be no open circuit because the current can still flow through the barrier layer. In this case, the void growth will lead to resistance increase. When the resistance increases to the critical level, the interconnect wire is considered to be failed. The growth time for late failure is

$$\displaystyle \begin{aligned} t_{\text{growth}}=\frac{\Delta r(t)}{v_d\left[\dfrac {\rho _{Ta}} {h_{Ta}\left( 2H+W\right) }-\dfrac {\rho _{Cu}} {HW}\right]} {} \end{aligned} $$

where ρ Ta and ρ Cu are the resistivity of tantalum (the barrier liner material) and copper, respectively. W is the line width, H is the copper thickness, and h Ta is the liner layer thickness.

However, the void may saturate before reaching the critical void length. The saturation length is expressed in [18] as

$$\displaystyle \begin{aligned} L_{ss}=L_{\text{line}}\times\left[\frac{\sigma_T}{B}+\frac{eZ\rho jL}{2B\Omega}\right] {} \end{aligned} $$

where L ss is the void saturated length, L line is the total length of the wire, and σ T is thermal stress. Void growth may stop before the calculated t growth because of the saturated void. If it happens, we treat the wire as immortal or its lifetime is larger than the target lifetime.

4.2 Transient EM Analysis for a Multi-Segment Interconnect Wire

One important aspect of transient EM analysis is calculating the lifetime of a given wire and its electrical conditions. If the increased resistance of the nucleated branch exceeds a threshold, the interconnect tree is marked as failed.

To compute the lifetime t life of a given wire, we need to make sure that the wire is mortal and Eq. (5) is not satisfied. If a target lifetime t target is given, the analysis method will give the resistance change ΔR at the target lifetime.

For those mortal wires, we start with time t = 1000 years and use bisection method to find t nuc. The transient hydrostatic stress will be computed by Eq. (11). Once the stress of one segment hits the critical stress, the wire is deemed as nucleated.

Then we need to determine if the wire is void incubation phase immortal. If the saturated void length is less than the critical length, the incubation time (eventually the lifetime) becomes infinite and the resistance remains unchanged.

Otherwise, the failure mode of the wire should be determined by looking at the current direction in the cathode node based on the patterns in Fig. 4.

If the wire is in the early failure mode, then the wire will become an open circuit: the whole interconnect tree will be disconnected from another interconnect wire as shown in Fig. 6a. For the wire in the late failure mode, we have another solution. The wire resistance change will be incurred and the growth time will be computed when the resistance change reaches the threshold as shown in Fig. 6b. If the target lifetime is given, then the wire resistance change ΔR will be computed at the target lifetime.

Fig. 6
figure 6

The electrical impact of different failure mechanisms on the interconnect wires: (a) early failure mode; (b) late failure mode

5 EM Immortality Constrained Optimization for Multi-Segment Interconnects

Study and experimental data show that the current-induced stress developed in the individual segments within an interconnect tree is not independent [14, 29]. In other words, if we just look at the current density for each segment individually, it may appear as if all wire segments are immortal, but the whole interconnect tree could still be mortal. The reason is that the stress in one segment of an interconnect tree depends on other segments [28]. As discussed before, this issue has been resolved by the recently proposed fast EM immortality check method for general multi-segment interconnect wires [23].

In this section, we introduce the EM immortality constrained power grid wire-sizing optimization method considering multi-segment interconnect wires. It can be noticed that the new EM constraint will ensure that all the wires are EM immortal, so we call this method EM immortal power supply optimization.

5.1 Problem Formulation

Let G = {N, B} be a P/G network with n nodes N = {1, …, n} and b branches B = {1, …, b}. Each branch i in B connects two nodes i 1 and i 2 with current flowing from i 1 to i 2. l i and w i are the length and width of branch i, respectively. ρ is the sheet resistivity. The resistance r i of branch i is

$$\displaystyle \begin{aligned} r_i = \frac{V_{i_1} - V_{i_2}}{I_i} = \rho \frac{l_i}{w_i} \end{aligned} $$

5.1.1 Objective Function

The total routing area of a power grid network in terms of voltages, currents, and lengths of branches can be expressed as follows

$$\displaystyle \begin{aligned} f\left( V,I\right) =\sum _{i\in B}l_{i}w_{i}=\sum _{i\in B}\dfrac {\rho I_{i}l_{i}^{2}} {V_{i1}-V_{i2}} \end{aligned} $$

We notice that the objective function is linear for branch current variables I and nonlinear for node voltage variables V .

5.1.2 Constraints

The constraints that need to be satisfied for a reliable, working P/G network are shown as follows.

Voltage IR Drop Constraints

In order to ensure proper logic operation, the IR drop from the P/G pads to the nodes should be restricted. For each node, we must specify a threshold voltage

$$\displaystyle \begin{aligned} &V_{j}>V_{\text{min}}\;\mbox{ for power network} \end{aligned} $$

where V j is the nodal voltage and V min is the minimum required voltage for the power nodes.

Minimum Width Constraints

The widths of the P/G segments are technologically limited to the minimum width allowed for the layer where the segment lies in

$$\displaystyle \begin{aligned} w_{i}=\rho \dfrac {l_{i}I_{i}} {V_{i1}-V_{i2}}\geq w_{i,\text{min}} \end{aligned} $$

New Electromigration Constraints for Multi-Segment Interconnects

As described before, for a multi-segment interconnect m, the EM constraint should be satisfied

$$\displaystyle \begin{aligned} V_{crit, EM} > V_{E,m}-V_{\text{cat},m} \end{aligned} $$

where V E,m is the EM voltage for the mth interconnect tree, which is computed using Eq. (2). V cat,m is the cathode nodal voltage of that tree. Unlike previous methods whose branch currents are monitored and used as constants, in our new method, voltages are used as constraints. Thus, only the cathode node voltage for a whole interconnect tree needs to be monitored and no other complex calculations are required.

We remark that V E,m, which is defined in (2), is a function of both nodal voltage and total area of wires. As a result, it is a nonlinear function of the nodal voltage (as the area of a wire segment is a function of both nodal voltage and branch current as defined in the cost function (20)). But if we have the equal width constrains as shown below, then constraint (23) actually becomes a linear function of nodal voltage again. For many practical P/G networks, most wire segments in an interconnect tree indeed have the same width.

Equal Width Constraints

For typical chip layout designs, certain tree branches should have the same width. The constraint is w i = w k, which can be written as

$$\displaystyle \begin{aligned} \dfrac {V_{i1}-V_{i2}} {l_{i}I_{i}}=\dfrac {V_{k1}-V_{k2}} {l_{k}I_{k}} \end{aligned} $$

Kirchhoff’s Current Law (KCL)

For each node j, we have

$$\displaystyle \begin{aligned} \sum _{k\in B(j)}I_{k}=0 \end{aligned} $$

where B(j) is the set of branches incident on node j.

5.2 New EM Immortality Constrained P/G Optimization

The power grid optimization aims to minimize objective function (20) subjected to constraints (21)–(25). It will be referred as problem P. Problem P is a constrained nonlinear optimization problem.

5.2.1 Relaxed Two-Step Sequence of Linear Programming Solution

In the aforementioned optimization problem, we notice that the newly added EM constraint (23) is still linear in terms of nodal voltage. As a result, we can follow the relaxed two-phase iterative optimization process [8, 27] and apply the sequence of linear programming technique [27] to solve the relaxed problem. Specifically, we have two phases: the voltage solving phase (P-V phase) and the current solving phase (P-I phase).

P-V Optimization Phase

In this phase, we assume that all branch currents are fixed, then the objective function can be rewritten as

$$\displaystyle \begin{aligned} f(V)=\sum _{i\in B} \dfrac {\alpha _{i}} {V_{i1}-V_{i2}} \end{aligned} $$

where \(\alpha _{i}=\rho I_{i}l_{i}^{2}\), subject to constraints (21)–(24). We further restrict the changes of nodal voltages such that their current directions do not change during the optimization process

$$\displaystyle \begin{aligned} \dfrac {V_{i1}-V_{i2}} {I_{i}}\geq 0 \end{aligned} $$

Problem P-V is nonlinear; however, it can be converted to a sequence of linear programming problem. By taking the first-order Taylor’s expansion of Eq. (26) around the initial solution V 0, the linearized objective function can be written as

$$\displaystyle \begin{aligned} g\left( V\right) =\sum _{i\in B}\dfrac {2\alpha _{i}} {V_{i1}^{0}-V_{i2}^{0}}-\sum _{i\in B}\dfrac {\alpha _{i}} {\left( V_{i1}^{0}-V_{i2}^{0}\right) ^{2}}\left(V_{i1}-V_{i2}\right) \end{aligned} $$

Besides, an additional constraint will be added [27]

$$\displaystyle \begin{aligned} \xi \text{sign}(I_{i})\left(V_{i1}^{0}-V_{i2}^{0}\right) \leq \text{sign}((I_{i})\left(V_{i1}-V_{i2}\right) \end{aligned} $$

where \(\xi \in \left ( 0,1\right )\) is a restriction factor, which will be selected by some trials and experience and sign(x) is the sign function.

Now, the procedure for solving problem P-V is transformed to the problem of repeatedly choosing ξ and minimizing \(g\left ( V\right )\) until the optimal solution is found. Theoretically, given \(g\left ( V_{m}\right )<g\left ( V_{m-1}\right )\), there always exists a ξ such that \(f\left ( V_{m}\right )<f\left ( V_{m-1}\right )\); however, one-dimensional line search method is a more efficient way to find the solution point. Specifically, given V m and V m−1, the search direction can be defined as d m = V m − V m−1. Line search finds an \(\alpha \in \left [ 0,1\right ]\) such that

$$\displaystyle \begin{aligned} f\left( \alpha d_{m}+V_{m-1}\right) <f\left( V_{m-1}\right) \end{aligned} $$

αd m + V m−1 becomes new V m for the next iteration.

P-I Optimization Phase

In this phase, we assume that all nodal voltages are fixed, so the objective function becomes

$$\displaystyle \begin{aligned} f(I)=\sum _{i\in B} \beta _{i}I_{i} \end{aligned} $$

where \(\beta _{i}=\dfrac {\rho l_{i}^{2}} {V_{i1}-V_{i2}}\), subject to constraints (22), (24), and (25). Similarly, we restrict the changes of current directions during the optimization process

$$\displaystyle \begin{aligned} \dfrac {I_{i}} {V_{i1}-V_{i2}} \geq 0 \end{aligned} $$

As can be seen, problem P-I is a linear programming problem.

5.2.2 New EM Immortality Constrained P/G Optimization Algorithm

The new EM immortality constrained P/G optimization starts with an initial feasible solution. We iteratively solve P-V and P-I. The global minimum of convex problem P-V will be achieved by performing several linear programming processes iteratively. The entire EM immortality constrained power grid network optimization procedure is summarized as Algorithm 1.

Algorithm 1 New EM immortality constrained P/G wire-sizing algorithm

In practice, only a few linear programmings are needed to reach the optimum solution. Thus the time complexity of our method is proportional to the complexity of linear programming.

6 EM Lifetime Constrained Optimization

In the previous sections, we discussed the power grid sizing optimization ensuring none of the interconnect trees fails based on the voltage-based EM immortality check. However, such EM constraint may be too conservative because in reality, some wires can be allowed to have EM failure as long as the power grid network is still functional (its IR drop is still less than the given threshold) at the target lifetime (e.g., 10 years).

6.1 New EM Lifetime Constrained Optimization Flow

In this section, we propose a new EM lifetime constrained P/G wire sizing optimization method in which some segments of multi-segment interconnect wires will be allowed to fail or to age. The impacts of these segments in terms of resistance change or even wire openings will be explicitly considered and modeled. Such aging-aware EM optimization essentially takes the EM aging-induced impacts or guard bands into account so that the designed P/G networks can still function nominally during the target lifetime. In this work, we only consider void formation, which is the dominant EM failure effect and will lead to an increase in resistance.

The new optimization flow is shown in Fig. 7. In this new flow, we first check whether a given power supply network can be optimized using Algorithm 1. If the optimization fails due to EM constraint, then the lifetime of all the interconnect trees will be computed based on the EM lifetime estimation method. We have several scenarios to discuss before we perform the optimization again. Let us define t life,m as the lifetime of the mth interconnect tree and t target as the target lifetime.

Fig. 7
figure 7

Flowchart of the EM lifetime constrained P/G optimization process

If V E,m − V cat,m > V crit,EM and t life,m < t target

The mth interconnect wire will be marked as a failed wire. Then we have the following changes for the wire before the next round of optimization.

If it is an early failure case, the cathode node of the wire segment connected by the failed via will be disconnected, which is called wire disconnection. The failure cases will depend on the current directions around the cathode node. Also the disconnection will depend on whether the void growth can eventually reach the critical void size or not as discussed in Sect. 4.1.

If it is a late failure case, the wire segment associated with the cathode node will have a resistance change. The specific resistance change for each failed segment will be calculated based on the target lifetime using our EM lifetime estimation method.

If an interconnect tree is marked as failed, then its EM constraint will be disabled as we do not need to consider its immortality anymore.

If V E,m − V cat,m > V crit,EM and t life,m > t target

The lifetime of interconnect wire still meets the target lifetime even though it will have void nucleation and resistance change. This also includes the case in which void growth saturates before its size reaches the critical void size. The wire still works since the current can flow through the barrier layer.

The existing V E,m − V cat,m value is used as the new EM constraint (defined as V E,m,next − V cat,m,next) for the mth wire only: V E,m − V cat,m < V E,m,next − V cat,m,next. This is called constraint relaxation. The rational behind it is that we expect the EM status of this wire to become worse during the next optimization so its lifetime will not change too much and still meet the given lifetime after the follow-up optimizations.

After resistance change, or wire disconnection, or constraint relaxation, a new round of SLP programming optimization, which is similar to Algorithm 1, is carried out.

7 Summary

In this chapter, a new P/G network sizing technique is presented, which is based on a voltage-based EM immortality check method for general multi-segment interconnect wires and a physics-based EM assessment technique for fast time to failure analysis. The new P/G optimization problem subject to the voltage IR drop and new EM constraints can still be formulated as an efficient sequence of linear programming problem, and will ensure that none of the wires fails if all the constraints are satisfied. To mitigate the overly conservative nature of the optimization formulation, the EM-induced aging effects on power supply networks for a target lifetime are further considered and an EM lifetime constrained optimization method is demonstrated, which allows some short-lifetime wires to fail and optimizes the rest of the wires. The new methods can effectively reduce the area of the power grid networks while ensuring reliability in terms of immortality or target lifetime, which is not the case for the existing current density constrained P/G optimization methods.