Abstract
This chapter proposes a selective flipflop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flipflop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timingcritical components under severe impact of runtime variations. As flipflops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the overall system lifetime. In the proposed method, we first extend the standard cell libraries by adding optimized versions of the flipflops designed for better resiliency against severe Bias Temperature Instability (BTI) impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the agingcritical and voltagedrop critical flipflops of the circuit with optimized versions to improve the timing and reliability of the entire circuit in a costeffective way. Simulation results show that incorporating the optimized flipflops in a processor can prolong the circuit lifetime by 36.9%, which translates into better reliability.
This chapter is organized as follows. Section 1 introduces widevoltage operation reliability issues and motivates the proposed selective flipflop optimization approach. The impacts of runtime variations on flipflops are explained in Sect. 2. Consequently, Sect. 3 presents celllevel optimization of the flipflops. The proposed selective flipflop optimization methodology is described in Sect. 4, and optimization results are discussed in Sect. 5. Finally, Sect. 7 concludes the chapter.
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1 Introduction, Motivation, and Contributions
VLSI circuits are influenced by several sources of process and runtime variabilities [16]. Among them, supply voltage fluctuation and transistor aging due to BTI are the most important factors [2, 30, 36]. They degrade the performance of VLSI circuits by increasing the delay, and consequently deteriorate lifetime.
The impacts of both voltagedrop and aging are significant on sequential elements such as flipflops and latches. Due to particular aspects of flipflops, such as the internal feedback structure, degradation of the transistors of a flipflop as well as supply voltage fluctuation may lead to serious timing degradation or even functional failure (inability to capture the input independent of timing) [24]. Furthermore, many flipflops are on the critical paths of a circuit because logic synthesis tools balance the delays of circuit paths to achieve the best performance, area, and power. Therefore, it is necessary to employ designtime mitigation techniques to consider and control such gradual degradation, e.g. by adding appropriate timing margins (aging and voltagedrop guardband) [20, 28].
Our analysis shows that in a typical digital design such as a microprocessor, based on the functionality of different components, some flipflops operate under static or nearstatic BTI stress, irrespective of the workload. These flipflops experience large timing degradation because the flipflop input Signal Probability (SP) is very close to 0.0 or 1.0. Being subject to severe BTI stress, the aforementioned flipflops degrade faster, imposing a large aging guardband to the entire circuit. Flipflops also experience a large temporally localized voltagedrop, because they are synchronized with the clock edge and supposedly operate at the same time (at clock edge), hence, drawing substantial current leading to a significant voltagedrop over Power Delivery Network (PDN) [22]. Moreover, recent studies have shown that the voltagedrop impact gets more severe by technology scaling [2, 21, 38]. Therefore, in a conventional design flow, costly voltagedrop timing guardband is considered for reliable circuit operation [22].
In this chapter, we explore methods to improve circuit reliability by addressing the timing degradation of flipflops under severe aging^{Footnote 1} and voltagedrop, i.e. selective flipflop optimization. The idea is to find timingcritical flipflops under high aging and/or voltagedrop impact, and selectively reoptimize them for operating under such stress by appropriately sizing their transistors. This effectively improves the reliability and lifetime of circuits without imposing much overhead, because these flipflops constitute a small portion of all flipflops.
Simulation results obtained by applying the proposed method to a processor show that the flipflops optimized with the proposed method exhibit much less delay degradation, while imposing less than 0.1% leakage power overhead to the processor. As a result, the required timing guardband of the processor using the proposed method is significantly less compared to the original processor. Therefore, given a specific clock period, the optimized processor design with the proposed method has 36.9% longer lifetime and better reliability compared to the original processor design.
2 Variability Impact on FlipFlops
2.1 FlipFlop Timing
Flipflop timing metrics such as setuptime (U), holdtime (H), clocktoq (D _{CQ}), and datatoq (D _{DQ}) are well discussed in [31, 34]. When the setuptime is large enough, the clocktoq value is almost constant, but further reduction of the setuptime will increase the clocktoq value monotonously until a value after which the flipflop is unable to capture and latch the input [31]. Based on this, the optimum setuptime is defined as the setuptime value which causes the clocktoq value to increase by 10% from its minimum value [32]. Moreover, each flipflop has two internal paths; one for transferring the input state “zero” to the output i.e. HightoLow (HL) input transition, and the other for transferring the input state “one” to the output i.e. LowtoHigh (LH) input transition. Basically, the timing parameters for these two internal paths can be different [24] as shown in Fig. 1, meaning that there are two sets of timing parameters for internal LH and HL paths of a flipflop:
Flipflop delay should be defined such that the correct functionality of the flipflop will be guaranteed, disregard of the transition. Therefore, we define the flipflop delay as the summation of the worst setuptime and the worst clocktoq of both transitions as shown in Fig. 1.
This guarantees that in both transitions the input signal is correctly captured and propagated to the flipflop output.
2.2 Runtime Variation Impacts on FlipFlops
Several parameters such as supply voltage, workload, and temperature affect the performance of flipflops in a circuit. Parameters such as temperature and supply voltage affect all the transistors of a flipflop in the same way, whereas the impact of the input SP is different for the transistors of a flipflop [23]. This results in an asymmetric aging of transistors according to their stress duty cycles. Therefore, the delay degradation of internal LH and HL paths inside an aged flipflop depends on the input SP [24].
In the C2MOS flipflop^{Footnote 2} depicted in Fig. 2a, the internal LH and HL paths consist of two separate groups of transistors, which makes the aging of these two paths independent according to the input SP. Figure 2b illustrates the delay of LH and HL transitions of an aged C2MOS flipflop [31] for different input SPs. When the flipflop is aged under input SP = 0.0 (SP0), the worst delay degradation happens on the flipflop HL path; however, the delay of the flipflop LH path is only slightly affected. On the other hand, an aging under input SP = 1.0 (SP1) greatly degrades the delay of the flipflop LH path while slightly affecting the delay of the flipflop HL path. For moderate aging condition, i.e. 0.1 < SP < 0.9, the delay degradation of both LH and HL paths is moderate. The reason is that under SP0 and SP1 conditions, Static BTI (SBTI) asymmetrically alters the threshold voltages leading to unbalanced aging of LH and HL paths of the flipflop as the stress duty cycle of some transistors is 1.0, i.e., always under BTI stress. However, in moderate aging condition, the transistors can partially recover as the stress duty cycle is less than 1.0.
The impact of supply voltage fluctuation on the flipflops of a circuit depends on the workload variation and dynamic power consumption of the circuit. Therefore, each flipflop may experience a specific amount of voltagedrop. A voltagedrop causes performance degradation of the flipflops, which is typically larger than the degradation of simpler combinational gates in the standard cell library. Figure 3 compares the impact of a voltagedrop up to 10% on the delay of an aged flipflop and an aged inverter. Compared to a novoltagedrop condition, the delay of the flipflop increases by 23.6% whereas the delay of the inverter is increased by 15%.
Moreover, the flipflops of a circuit generally experience higher amount of voltagedrop compared to combinational gates [37]. As a result of temporally localized switching of flipflops at the positive (or negative) edge of clock signal, the instantaneous current drawn from PDN at the synchronized clock edge is comparatively high. This leads to high voltagedrop at the clock edge, when the flipflops are processing their input signals. This peak current consumption is damped over the rest of the clock period, when the combinational cells are active. Therefore, in this work we focus on dealing with the impact of voltage fluctuation on the flipflops.
Temporal and spatial temperature variations can also affect the circuit performance. The temporal temperature change could be rather high and has been the subject of research since it affects the reliability of the VLSI circuits. It is demonstrated in [17] that the circuit performance can be changed by up to 10% for 110^{∘}C temperature variation. Therefore, in order to meet the reliability constraints, the circuit timing should be adjusted according to the worst temperature corner, which is typically at high temperature. Onchip spatial temperature gradient puts different stress on circuit components across a chip. The amount of onchip spatial temperature difference (only on cores) based on simulation [3, 7], sensor measurements [33], and thermal camera [3] is reported to be up to ∼30^{∘}C. Since the delay change is approximately 4% for every 40^{∘}C [17, 29], the overall difference between the delay degradation of core flipflops due to such spatial temperature gradient is expected to be less than 3%, and hence, much smaller compared to voltagedrop variation [11].
The combined impact of voltagedrop and aging significantly degrades the performance of flipflops. As an example, the delay of a fresh flipflop optimized with balanced HL/LH delay increases from 98.5 ps to 165.7 ps due to the combined impact of voltagedrop (10%) and SBTI (5years under SP0). This is equivalent to 68% delay increase. If such a flipflop is in a critical path of the circuit, a large timing guardband is required for timing closure considering the reliability constraints. Therefore, it is necessary to find such flipflops at designtime and optimize them for operating under such conditions.
2.3 Significance of FlipFlops in Circuit Reliability
In a properly designed circuit, the timing of circuit paths are balanced during the synthesis process. Therefore, many flipflops are timingcritical as they lie on the circuit critical paths. Studies [12, 37] have shown that in VLSI circuits, some flipflops are under severe static BTI leading to a large timing degradation over time. Furthermore, the impact of voltagedrop on flipflops could be very high as a result of localized power consumption at a specific time (e.g. positive clock edge) or at a specific location on the circuit layout.
The large impact of SBTI and voltagedrop on flipflops has a significant impact on the reliability of a circuit when such flipflops are timingcritical. In order to investigate the likelihood of having such a scenario in a typical digital design, we use the flow presented in Sect. 4 to extract the voltagedrop and the aging of the Leon3 flipflops by executing six MiBench workloads [15] namely stringsearch, qsort, basicmath, bitcount, fft, and crc32 on Leon3 processor [10]. In order to be fair, we excluded the flipflops belonging to the parts which are not exercised by the employed workloads such as interrupt handler, timers, and UART controller. The synthesized netlist of the Leon3 processor has 2352 flipflops, but the results demonstrated in this section contain only 1686 flipflops belonging to the parts which are exercised by all employed workloads.
Figure 4a demonstrates the input SP distribution of the aforementioned 1686 flipflops. The results show that 181 flipflops always experience input SP0, whereas 29 flipflops are under input SP1. Our analysis shows that the flipflops with such behavior typically belong to either the error checking and exception handling registers or higher bits of address registers which are constant due to temporal and spatial locality of the executed instructions. Besides, the SP of a considerable number of flipflops is very close to either 0.0 or 1.0. Please note that the results reported in Fig. 4a are the average of six employed workloads, and hence, the flipflops with SP = 0 or SP = 1 have such SP across all executed workloads. Similar experiment has been carried out in [18] to study the impact of workload in real systems, which shows that some flipflops are always under SBTI across different workloads.
Figure 4b shows the distribution of the maximum voltagedrop impacting the flipflops of Leon3 processor compared to the peak voltagedrop across all the executed workloads. Please note that it is necessary to consider the maximum voltagedrop over the execution of all workloads, because it eventually impacts the flipflop characteristics. A significant portion of flipflops experience on average 41% of the maximum amount of voltagedrop; however, there are flipflops at the right side tail of the distribution which experience large voltagedrop comparable to the maximum voltagedrop in the circuit.
According to the observations in Fig. 4, there are flipflops experiencing both SBTI and high voltagedrop which leads to highdegradation. If such flipflops are on a critical path of the processor (i.e. timingcritical flipflops), the degradation of the flipflops should be reflected in the timing guardband of the circuit. Timingcritical flipflops can be categorized into different groups based on the impact of voltagedrop and aging as follows:

low voltagedrop and low aging,

low voltagedrop but SBTI aging (SP0/SP1)*

high voltagedrop but typical aging*

high voltagedrop and SBTI aging (SP0/SP1)*
Therefore, we propose to generate flipflops specifically optimized for such highdegradation conditions (marked by *) and add them to the standard cell library. Using the proposed flow in Sect. 4, we determine such highdegradation and timingcritical flipflops and replace them with the optimized versions to improve the timing and reliability of the circuit.
3 ReliabilityAware FlipFlop Design
In a typical reliabilityaware circuit design, one should consider the delay of the elements under variation impacts to ensure the correct functionality of the circuit during the expected lifetime. Therefore, higher delay degradation of timingcritical flipflops imposes a large timing guardband. In our proposed methodology, we create optimized versions of the flipflops for different stress conditions based on aging and voltage fluctuations, and use these optimized versions only when a flipflop is timingcritical and subject to such stress conditions to avoid unnecessary over design. This means that in the cell library, we add the following resilient versions of the flipflops:

Agingresilient flipflops, optimized for different aging corners (SP0 and SP1),

Voltagedrop resilient flipflops, optimized to have lower performance degradation under voltage fluctuation,

Aging and voltagedrop resilient flipflops.
3.1 AgingResilient FlipFlop Design
When the fresh delays of internal paths of a flipflop (i.e., LH and HL paths) are designed to be similar (depicted as solid lines in Fig. 5), the internal path with higher degradation rate eventually becomes dominant and determines the total delay of the flipflop. In this case, a significant aging in flipflop characteristics is observed over time (corresponding to the internal path with higher degradation). On the other hand, if the internal path with higher degradation rate is initially faster (by design) than the internal path with lower degradation rate, the dominant internal path would be the slower one, and hence the higher degradation rate of the faster internal path is masked. Consequently, the overall aging of the flipflop would be rather small. The delay of the optimized flipflop, shown in Fig. 5 by dashed lines, exhibits such characteristics. The postaging delay of the optimized flipflop would increase by ∼10 ps, which is much lower than ∼40 ps increase in the delay of the original flipflop. We exploit this method for designing agingresilient flipflops.
In order to decrease the overall BTIinduced aging inflicted to a flipflop, our proposed method balances the delay of internal HL and LH paths of the flipflop for postaging state of the flipflop, by resizing the transistors of internal HL and LH paths. In other words, the proposed method increases the fresh delay (t = 0) of the flipflop internal path which has lower degradation rate in order to compensate the overall degradation of the flipflop after aging. Although the fresh delay of the optimized flipflop might be slightly larger compared to the fresh delay of the original flipflop, the overall delay of the optimized flipflop considering the aginginduced timing margin would be smaller than those of the original flipflop since the aging rate is much smaller.
Please note that this method reduces the degradation for a given SP, but inevitably worsens the aging at the other corners of SP. For example, if we optimize the flipflop for SP0, the degradation would be much higher if the optimized flipflop operates at SP1. Nevertheless, these flipflops under SBTI will not operate at other SP corners, because their SP is determined by the circuit structure and functionality. Therefore, we only optimize for the given SP corner. This means that we intentionally sacrifice other corners, which never occur due to the specific functionality of the circuit, to gain a larger improvement.
3.2 VoltageDrop Resilient FlipFlop Design
Other than aging, which affects each flipflop transistor based on the input signal probability, a drop in the supply voltage of the flipflop slows down all flipflop transistors in the same way. However, a slight upsizing of specific transistors can compensate the degradation in the flipflop timing. Therefore, we evaluate the delay of the flipflop when operating under the impact of voltagedrop, and optimize the flipflop with the goal of improving the delay. Consequently, the optimized flipflop would have better timing at the cost of higher power consumption.
3.3 Aging and VoltageDrop Resilient FlipFlop Design
The degradation in the flipflop timing due to both SBTI and voltagedrop is very large. Such timing degradation may not be effectively compensated by resizing the transistors within a flipflop area without upsizing the entire flipflop. Therefore, in addition to targeting for better timing under the impact of the aging and voltagedrop, we allow the optimization algorithm to increase the area of the flipflop by a small percentage. Please note that an extra Engineering Change Order (ECO) might be needed to replace the original flipflop with the optimized version in this case. However, since there exist only a few flipflops under such degradation it would not be an issue to perform an ECO on placement.
3.4 Problem Formulation for FlipFlop Resiliency Optimization
The delay of a flipflop under a specific working condition (including temperature, voltage, and input SP) can be presented as a function of the transistors’ widths:
where [w _{i}] is a vector containing the width of flipflop transistors. Here, delay is the delay (Datatoq) of the flipflop, according to Eq. (1), under variation impact, which could be SBTI stress, voltagedrop, or both depending on the optimization approach.
The delay function f is a complicated function of transistors’ widths. Our experimental results for flipflops with different sizing show that f cannot be presented with any general linear function. Therefore, we use Sequential Quadratic Programming (SQP) which is a nonlinear programming technique [19]. In SQP, the problem is converted into quadratic subproblems and solved in order to find a better sizing in each iteration. For this purpose, we follow an iterative approach in order to minimize the delay of Eq. (2). Given an initial sizing, the delay function f is approximated with a quadratic function:
where ▽ f(W) and H _{f}(W) are the gradient and the Hessian of the delay function f, respectively. Minimizing the quadratic approximation of Eq. (3), with respect to some constraints, which will be discussed later in this section, yields an optimized transistor sizing. Thereafter, the obtained sizing is used as the initial sizing, and a new iteration is launched. This cycle continues until the optimization reaches the required precision, i.e. the difference between the optimized delays of two consecutive iterations becomes smaller than a predefined threshold 𝜖 _{delay}. Therefore, the solver continues by checking the precision of the resulting delay:
where delay_{i} represents the delay of ith iteration.
Another reason to use the quadratic approximation is that the optimum result of a linear problem always lies on the boundaries, while the optimum result of a quadratic problem can be any point within the boundaries as well as the boundaries themselves. In Sect. 5, we demonstrate that the optimum result does not necessarily lie on the boundaries, and hence a nonlinear programming technique is needed to find a better result. Table 1 summarizes the optimization problem.
Several constraints are applied to the optimization problem, relating to transistors size, flipflop area, and leakage. The first constraint shown in Table 1 limits the minimum size of transistors. The second constraint limits the area of the optimized flipflop. In case of optimizing for SBTI or voltagedrop, we consider λ = 0 to keep the flipflop area within the area of the original flipflop which also facilitates keeping the aspect ratio almost equal to the aspect ratio of the original flipflop. This way, the optimized flipflop can easily replace the original flipflop without any layout modifications at the circuitlevel. This is achieved by limiting the summation of transistor widths w _{i}. However, for flipflops under SBTI and voltagedrop, we assume a λ > 0 value to compensate the delay degradation better. The third constraint sets an upper limit for the excessive leakage of the flipflop by parameter β. This constraint is applied to the optimization problem to limit the leakage power of the optimized flipflops within an acceptable range. The initial guess of optimization W _{0} is the optimum sizing for minimum PDP in the fresh state.
3.5 ReliabilityAware FlipFlop Optimization Flow
Figure 6 presents our proposed reliabilityaware optimization flow. For a given input SP, the SP of all transistors are once calculated using SPICE simulations. Afterwards, based on the extracted SP for transistors and the operating corner of the flipflop (temperature, supply voltage, etc.), the BTIinduced threshold voltage shifts of all transistors (ΔV _{th}) are obtained. Then, the ΔV _{th} values are backannotated into the original flipflop SPICE netlist, and the SPICE netlist of aged flipflop is generated.
In each SQP iteration, the quadratic subproblems are created and solved to generate further improved flipflop sizing. Subsequently, the new sizing is backannotated into the aged flipflop netlist extracted before, and a new aged flipflop with the given sizing is generated. Then, Cadence Virtuoso Liberate [6] is used to characterize the new flipflop and extract its delay and power consumption. When the improvement is small enough and the condition in Eq. (4) is met, the SQP method terminates and returns the last sizing as the optimum solution for the problem.
As the process is executed at a specific supply voltage (V _{dd}), it can inherently be used to optimize for a voltagedrop as well, when the given supply voltage includes the impact of the voltagedrop. We can also create voltagedrop resilient version of a flipflop for typical aging, by considering input SP of 0.5. Therefore, we execute the flow presented in Fig. 6 for these conditions in order to create variationresilient versions of the flipflop, assuming a supply voltage of V _{dd} and a maximum voltagedrop of R%:
Supply voltage (V )  Aging condition  

Aging  V _{ dd }  SBTI (SP0, SP1) 
Voltagedrop 
 Typical aging (SP = 0.5) 
Aging and voltagedrop 
 SBTI (SP0, SP1) 
After optimization process, it is necessary to recharacterize the flipflops for different supply voltage ( to V _{dd}) and aging conditions (0 ≤SP ≤ 1). The characterization results are then used to obtain overall circuit timing under supply voltage fluctuation and aging impacts.
4 Selective FlipFlop Optimization
This section explains how the optimized flipflops in Sect. 3 can be employed to improve the reliability of a circuit. The idea is to find the flipflops affected by SBTI and/or voltagedrop impacts which are also influential on circuit reliability, i.e. the timingcritical flipflops, and replace them with the optimized versions. The reason for this selective flipflop optimization is that the reliabilityaware flipflop optimization is costly in terms of leakage overhead per flipflop. Therefore, flipflop replacement should be done only for the timingcritical flipflops which experience SBTI and/or large voltagedrop to be costeffective. Since they constitute a small subset of the all flipflops in the design, the proposed method is able to reduce the overall timing guardband in a costeffective way.
The overall flow of the proposed selective flipflop optimization methodology is presented in Fig. 7. The flow uses the results of the Synthesis and Place & Route steps of a VLSI design flow and is composed of (I) Aging and VoltageDrop Analysis and (II) Selective Flipflop Replacement steps. The optimization flow updates the gatelevel netlist and the circuit layout to improve the reliability of the circuit under voltagedrop and aging impacts. The outputs of the optimization method can be further used in the rest of the VLSI design flow. Therefore, the proposed method is transparent to the VLSI design flow and can be easily integrated into it.
4.1 Aging and VoltageDrop Analysis
In this step, the results of Synthesis and Place & Route steps of the VLSI design flow are used to discover the flipflops which are agingcritical, voltagedrop critical, and timingcritical.
Agingcritical flipflops are those flipflops which experience large impact of aging, i.e. flipflops under SBTI. To find the agingcritical flipflops we need to extract the SP of the flipflops. Therefore, we perform a gatelevel simulation running some representative workloads. The representative workloads are pieces of workloads which are typically executed on the circuit. The result of the gatelevel simulation is the Voltage Change Dump (VCD) of all nets inside the circuit. Based on this information we can collect SP of all flipflops and determine the agingcritical flipflops.
Dynamic power profiles of circuit components can be extracted from the VCD reports. We estimate the dynamic voltagedrop in the circuit based on the power profiles and the layout and packaging of the circuit. This accounts for the resistive and inductive components of the voltage fluctuation. We generate a voltagedrop map of the circuit by evaluating the maximum voltagedrop of each cell (gates, flipflops, etc.) over the time and over different workloads. As a result, we find the maximum amount of voltagedrop that each flipflop experiences over time. Accordingly, the flipflops which experience a large amount of voltagedrop are extracted.
Furthermore, the gatelevel simulation results are used to perform a voltagedrop and agingaware timing analysis which obtains the delay of circuit paths under variability impacts. We extended the agingaware timing analysis in [8] by considering voltagedrop related information. This is done by characterizing the cells at two different supply voltages: the nominal V _{dd} and the supply voltage considering the maximum drop . Then, for each gate/flipflop in the gatelevel netlist, based on the amount of voltagedrop on the gate, we perform a linear interpolation among the standard cell library entries for two supply voltages and find the corresponding timing information. The linear interpolation is a valid method under the assumption of limited change in the supply voltage, as shown in Fig. 3. For a more aggressive voltage fluctuation, it could be necessary to characterize the standard cell libraries for a few intermediate supply voltage values and employ a PCHIP method. Accordingly, we find the timingcritical flipflops, which are parts of the critical and nearcritical paths of the circuit considering the impact of variations.
4.2 Selective FlipFlop Replacement
In the selective flipflop replacement step, we replace the flipflops which are timingcritical, agingcritical, or voltagedropcritical with their optimized counterparts for such aging and/or voltagedrop conditions. Although a small portion of the flipflops are replaced during the flipflop replacement process, the circuit layout, timing, and power properties change since the replaced flipflops are timingcritical and may have different area and power characteristics. Therefore, the proposed flipflop replacement is an iterative process which replaces a number of flipflops with the optimized versions in each iteration. The iterative process continues until no flipflop needs to be replaced by an optimized version anymore.
In iteration i of the method, we assume that the circuit delay is D ^{i} based on timing analysis results, and \(d_j^i\) is the maximum delay of the paths terminating at flipflop j (including the delay of the flipflop as well). Therefore, in each iteration:

1.
We choose the timingcritical flipflops with a timing slack value of less than k% of the circuit delay, i.e. when:

2.
Among these flipflops, those which are also included in the agingcritical and/or voltagedropcritical flipflops, are replaced with the optimized versions.

3.
A trial voltagedrop and agingaware timing analysis is performed and the circuit delay (D ^{i++}) is determined considering the replaced flipflops.

4.
We keep the optimized flipflops only when the corresponding path delay of the flipflops before optimization is larger than a percentage of the evaluated circuit delay (D ^{i++}):
$$\displaystyle \begin{aligned} d_j^i > r \times D^{i++} \Longrightarrow FF_j\rightarrow FF_{j,opt}. \end{aligned} $$(5)The rest of the updated flipflops in this iteration are rolled back to the original versions. Please note that we also consider a ratio r < 1 into Eq. (5) to compensate for the calculation errors due to simulation.

5.
The layout and gatelevel netlist of the circuit are updated. The layout is only updated if a cell with larger area is used (particularly applicable to the flipflops under both aging and voltagedrop as explained in Sect. 3).

6.
In case any flipflop is replaced by an optimized version during this iteration, we need to start a new iteration because the timing and power specification of the circuit are modified. This is done by reexecuting the aging and voltagedrop analysis, as explained in Sect. 4.1. The gatelevel simulation, which is a time consuming process, does not need to be repeated as its results are not affected by the flipflop replacement.
The above flow replaces minimum number of flipflops with the optimized versions and impose minimum amount of overhead to the circuit. In our simulations the flow is terminated within a few iterations, since the changes in the circuit layout, power, and timing are not extensive.
5 Results and Discussions
In this section, we evaluate the efficiency of the proposed selective flipflop optimization based on simulation results.
5.1 Simulation Setup
We applied the method to several flipflop topologies, namely C2MOS latch, Dynamic/Static Single Transistor Clocked latch (DSTC/SSTC), and SemiDynamic flipflop (SDFF) [31]. The flipflops are implemented using 45 nm Bulk CMOS Predictive Technology Model (PTM) transistors [39]. All flipflops are initially optimized for the minimum PDP in the fresh state (original design). The aging parameters of the model proposed in [4] are tuned so that the postaging delay of a FanOut 4 (FO4) inverter increases by 10% at SP = 0.5 over 5 years. For delay and leakage measurements, the output load of flipflops is set to FO4, and the cells are characterized at room temperature and at different supply voltages, ranging from 80 to 100% of the nominal supply voltage of the technology node.
We used Leon3 processor as a case study for our proposed method. We used Nangate 45 nm open cell library for combinational logic, and aging assumptions are the same as described at the beginning of this section. The processor is synthesized using Synopsys Design Compiler and placement and routing is done using Cadence EDI [5].
We executed various MiBench workloads on the synthesized Leon3 processor and extracted the VCD files. Based on the VCD files, the SP of each node of the synthesized circuit is calculated and the power consumption of the gates and flipflops is calculated using Synopsys Power Compiler. The voltagedrop map of the processor is also extracted using VoltSpot tool [38], which is able to extract the voltagedrop caused by both resistive and inductive components.
Please note that the proposed technique is not restricted to a specific working condition or flipflop topology. We proceed with presenting detailed results and analysis for a C2MOS flipflop. Then, we discuss the results for other types of flipflops concisely. Afterwards, the dependency of the improvement achieved by the proposed method to the excessive leakage will be investigated. At the end of this section, the impact of using optimized flipflops on a Leon3 processor lifetime will be demonstrated.
5.2 Detailed Optimization Results of C2MOS FlipFlop
We apply the proposed optimization flow presented in Sect. 3.5 (see Fig. 6) to C2MOS flipflop design to create optimized flipflops for aging and voltagedrop resilience. In order to create the agingresilient versions of the C2MOS flipflop, we let the optimizer to consider designs with up to 25% more leakage compared to the original flipflop by setting the coefficient β in Table 1 to 0.25. At this point, we limit the area of the flipflop to the area of the original flipflop, i.e. λ = 0. Please note that the total overhead of the leakage power for the entire circuit would be negligible since the number of optimized flipflops in the design would be limited. For example, if according to Sect. 2.3, 12.45% of flipflops are working under SBTI, and the leakage overhead of an optimized flipflop would be less than 25%, the leakage overhead imposed on the flipflops would be at most 3.11% (much less overhead when considering the entire processor design). The aging and voltagedrop resilient version of the C2MOS flipflop can be created by assuming an extra area up to 20% and more leakage overhead. For this, we assume λ = 0.2, β = 1. Using the extra area, the optimizer is able to find a better design for those flipflops which are timingcritical and are under large impact of aging and voltagedrop. Since these flipflops are very rare, but have significant impact on the overall processor lifetime and reliability, it is effective to spend more area for large reliability and lifetime gains.
Table 2 compares the characteristics of an original and optimized C2MOS flipflop (such as setuptime (U), clocktoq (D _{CQ}), datatoq (D _{DQ}), delay, and leakage) in three different optimization scenarios:
 Scenario 1:

postaging PDP, optimized for PDP in postaging.
 Scenario 2:

The proposed method (optimized for aging), in which the flipflop is optimized for aging resiliency, by minimizing its delay for postaging. The acceptable excessive area and leakage are 0% and 25%, respectively (β = 0.25, λ = 0).
 Scenario 3:

The proposed method (optimized for aging + vdrop), in which the flipflop is optimized for aging and voltagedrop resiliency, by minimizing its delay for postaging and under voltagedrop impact. The acceptable excessive area and leakage are 20 and 100%, respectively (β = 1, λ = 0.2).
The optimization results in Table 2 are reported for “fresh” state (no aging or voltagedrop), for “aged” state (under SBTI aging SP0 for 5 years), and for “aging + vdrop” state (when the flipflop is aged under SBTI for 5 years, and when the supply voltage is dropped by 10%). Setuptime, clocktoq, and datatoq values are presented for LH/HL transitions and the delay is calculated according to Sect. 2.1. The delay degradation is the relative postaging delay increase of a design compared to the fresh delay of the original design (marked as bold in the table):
Since the optimized flipflop will replace the corresponding flipflop in the design, the delay degradation is compared to the fresh delay of the original flipflop in order to give a better understanding of how close the aged delay of the optimized flipflop is to the fresh delay of the original design.
Basically, scenario 1 is similar to the methods proposed in many flipflop optimization methods such as [1, 13] in the sense that they consider a multiplication of energy and delay (e.g., the PDP or the Energy Delay Product (EDP)) as the optimization target. Scenario 1 is able to effectively reduce the PDP by increasing the delay and reducing the leakage, but this may result in an unacceptable timing for SBTI corners. Table 2 shows that due to not considering the flipflop delay as the optimization target, the PDP methods cannot find the optimum agingresilient sizing for SBTI corners.
As presented, for the original flipflop, the fresh delay of LH and HL paths is almost identical (see D _{DQ,LH} and D _{DQ,HL}), but after aging HL path is much slower than LH path. This leads to 35% delay degradation due to only aging and about 68% when aging and voltagedrop affect the flipflop. When this flipflop is optimized for scenario 1, the delay is not reduced well enough because the main concern is PDP not delay. On the other hand, in scenario 2 (proposed method, only for aging), the optimizer alters the sizing to equalize the postaging delay of the LH/HL paths to achieve the smallest possible postaging delay with respect to the constraints (119.4 ps). In this case, the postaging delay is increased by 21% compared to the fresh delay of the original flipflop. Also the leakage overhead is limited to 4.7%. Since the flipflop operates in SBTI zone, the switching rate of the flipflop is very small. This means that its dynamic power is almost negligible. Therefore, the total power in of flipflops under SBTI is determined by the leakage power.
Even though scenario 2’s design is much better for flipflops which are only under the aging impact compared to the original and the stateoftheart [1] flipflop designs, the impact of 10% voltagedrop is significant on the delay, i.e. 49% delay degradation. The flipflop optimization results for scenario 3 show that such flipflops are more resilient against both aging and voltagedrop impacts. These flipflops consume about 53% more leakage; however, the delay degradation is only 32% under both aging and voltagedrop. Please note that the number of flipflops under such condition is very small. Therefore, using flipflops optimized by scenario 3 has negligible impact on the overall processor power consumption.
5.3 Optimization Results for Other FlipFlops
Figure 8 provides the optimization results for a set of representative flipflops. It compares the delay and the leakage of the original and optimized flipflops, for both fresh and postaging states. All delay values are normalized to the fresh delay of the corresponding original flipflops (which are 114.8 ps for C2MOS, 28.5 ps for SDFF, and 71.0 ps for SSTC).
For C2MOS flipflop, the proposed method reduces the delay degradation in Eq. (6) to 21%, while the delay degradation of the original design is 35% (14% improvement). This flipflop has a symmetric structure, which means it can have balanced timing for LH/HL transitions (shown in Fig. 2b), while some flipflop topologies such as SDFF, always have an unbalanced timing for LH/HL transitions due to their internal structure. For example, in an SDFF, the delay of HL transition is always smaller than the LH transition. The reason is that, an intermediate precharged node in this flipflop should be discharged in LH transition in order to transfer the input “one” to the output, while for the HL transition no such discharging is required. Hence, the slower path is always the LH path. This may worsen the aging if it is coupled with unbalanced aging. For these flipflops, the optimizer minimizes the delay of the slower path by taking as much area as it can from the faster path, and giving the area to the slower path. For SDFF, this is attained with 15.8% additional leakage at SP0, but it leads to better SBTI resiliency.
5.4 DelayLeakage TradeOff
In order to understand the tradeoff between additional leakage and delay, we optimized a C2MOS flipflop with several excessive leakage amounts ranging from 0 to 50% (i.e. β ∈{0, 0.125, 0.25, 0.5}). As shown by Fig. 9, lower delay degradation can be achieved by allowing the optimization method to design flipflops with higher leakage. However, the improvement saturates as β increases. Hence, providing extra leakage to the optimizer is only beneficial until about 25%, because the improvement in the delay is not significant. Please note that the designed flipflops with looser leakage constraints, i.e. higher β, do not necessarily have very high leakage. As shown in Table 2, the optimized flipflop in scenario 2 (only aging) has only 4.7% extra leakage while providing much better resiliency against SBTI aging compared to the original flipflop and scenario 1 (stateoftheart work).
5.5 DelayArea TradeOff
The impact of a small amount of extra area on the resiliency of the flipflops against both aging and voltagedrop impacts is studied by changing parameter excessive area overhead λ (see Table 1). We run the optimization flow in Sect. 3 for λ ∈{0, 0.2} values and compare the results to the original flipflop design. Based on the results shown in Fig. 10, the flipflop designs with no extra area, i.e. scenario 2, exhibit good resiliency against aging; however, under the impact of 10% voltagedrop it has up to 49% delay degradation. Under the impact of voltagedrop, the flipflop designed with 20% extra area exhibits much better characteristics with maximum 32% delay degradation. This observation confirms that using flipflops with 20% extra area can be beneficial for the cases when both aging and voltagedrop impacts are severe.
5.6 CircuitLevel Results
The proposed selective flipflop optimization method presented in Sect. 4 is applied to Leon3 processor with the setup presented in Sect. 5.1 to evaluate the overall impact on the processor timing and reliability. The “original flipflop” designs are optimized for different output loads for minimum PDP in the fresh state, while the “optimized flipflop” designs for “aging” and “aging + vdrop” are obtained by applying the proposed method. Therefore, per each original flipflop design for a specific output load, there are different optimized designs for SBTI corners SP0 and SP1 as well as novdrop and maxvdrop conditions (according to Sect. 3.5).
The timing of Leon3 processor is evaluated using the “aging and voltagedrop analysis” step of the proposed flow (see Fig. 7). This incorporates using an improved version of an agingaware timing analysis tool [8] which also considers the impact of supply voltage variation as explained in Sect. 4.1. This timing analysis determines the processor delay under runtime variation impacts.
Figure 11 illustrates the timing of Leon3 flipflops on the processor layout as well as the calculated impacts of voltagedrop and aging on the processor timing. The presented plots are all normalized to the maximum values (maximum voltagedrop, maximum delay, maximum aging) for better visualization. Therefore, higher values (darker colors) represent a critical situation. Figure 11a presents voltagedrop of the flipflops extracted using the “aging and voltagedrop analysis” step. The voltagedrop values are normalized to the maximum voltagedrop value extracted during the simulations. As shown, many flipflops experience at least a moderate voltagedrop during the workload execution. However, the flipflops on the topleft corner of the layout experience heavy voltagedrop. The timing criticality of the flipflops is also shown in Fig. 11b. The flipflops with lower timing slack have values closer to 1.0 in this figure (darker). Interestingly, some of the flipflops on the topleft corner are also timingcritical. Additionally, the agingcriticality of the flipflops is presented in Fig. 11c. It is shown that many flipflops which are under SBTI are also timingcritical. Most importantly, a few timingcritical flipflops are affected by both aging and voltagedrop impacts.
Table 3 presents processor delays obtained in fresh state, i.e. no aging or voltagedrop, and when under aging and voltagedrop impacts. We compare the delay of original processor (before applying the proposed method) with the delay of the optimized processors, under runtime variation impacts (aging and voltagedrop) after 7 years. The results are reported for:

1.
“Original processor”: using only original flipflops,

2.
“Optimized processor for aging”: when only the impact of aging is considered during optimization,

3.
“Optimized processor for aging and voltagedrop”: when the impacts of aging and voltagedrop are considered during optimization.
The “original processor” is synthesized using the original flipflops designs in Table 2. Then, we apply the proposed selective flipflop optimization in two modes: (I) when only aging is considered, and (II) when both aging and voltagedrop are considered. This obtains two versions of the optimized processor, i.e. “Optimized processor for aging” and “Optimized processor for aging and voltagedrop.” In the optimization flow presented in Sect. 4.2, we assume k = 0.15. Therefore, all flipflops with a slack value less than 15% of the processor delay are assumed as timingcritical flipflops. Additionally, we assume r = 0.95, which means up to 5% calculation error guardband in the timing analysis method is acceptable. In fact, r value depends on the accuracy of the timing analysis method. After replacing the critical flipflops according to the proposed method, the processor delay is obtained again using the “aging and voltagedrop analysis” step.
According to the table, delay of the “original processor” is increased by 9.97% after 7 years. This translates into 138.6 ps timing guardband for 7 years of circuit operation, i.e. T _{clk} ≥ 1528.2 ps. The “optimized processor for aging” has better delay 1494.8 ps under the impacts of aging and voltagedrop which reduces the required timing guardband by 33.4 ps for 7 years of operation, hence optimizing the performance. Therefore, the degradation rate of this optimized processor is such that it can operate for 9.2 years (30.8% lifetime improvement), if it is used with the timing margins of T _{clk} = 1528.2 ps. Finally, the required timing guardband of “Optimized processor for aging and voltagedrop” is further reduced by 41.5 ps compared to the original processor. Therefore, the lifetime of the processor is improved by 36.9% (9.6 years).
The reason for the achieved improvements in Table 3 is explained by Fig. 12. Here, we only plotted the delay of timingcritical flipflops with a slack smaller than 15% of the processor delay (under aging and voltagedrop impacts). With this assumption, there are 261 timingcritical flipflops. Among the timingcritical flipflops, 92 flipflops are under SBTI impact (i.e. 0 ≤SP < 0.01 or 0.99 < SP ≤ 1), 235 flipflops experience at least 33% relative voltagedrop. After applying the selective flipflop optimization method, 96 flipflops are replaced with optimized versions, from which 39 flipflops are upsized (due to both aging and voltagedrop impact).
As the optimized flipflops constitute about 4% of all flipflops in Leon3, the overall leakage overhead with this method is 0.22% according to power analysis results using Synopsys Design Compiler. Moreover, there is virtually no dynamic power overhead because the replaced flipflops are mostly under SBTI impact and they rarely switch. The additional area overhead is also very negligible because only 39 flipflops are replaced by the upsized versions (less than 0.1% area overhead). The ECO process easily fits these flipflops into the existing layout by slightly moving other cells. Please note that the impact of the voltagedrop and aging on the driving logic paths is much less compared to the flipflops. Therefore, these paths are degraded at a much lower rate.
6 Comparison with the Related Work
Various methods have been proposed to address the impact of aging and voltagedrop on flipflops [1, 13, 23, 25]. For example, [1] proposes a method to improve flipflop reliability for a set of corners with different working conditions such as temperatures and voltages by altering the sizing of transistors. These studies mostly optimize flipflops for dynamic BTI stress condition, and flipflops under static BTI are mostly overlooked. As explained, the traditional optimization techniques such as optimization for the PDP, or EDP cannot effectively address the delay increase of flipflops under such stress. There are techniques to reduce the overall impact of voltagedrop on VLSI circuits by skewing the clock input of the flipflops at designtime in order to reduce the peak current at clock edge [9, 35]. However, these methods are not applicable to flipflops with zero (or close to zero) timing slack on the critical paths. The techniques at high abstraction level by softwareguided thread scheduling [27] or by voltage emergency prediction [26] also impose additional overhead at another abstraction level than circuitlevel, in order to address a circuitlevel problem.
7 Summary
In many cases, NTC circuits are required to operate over a wide voltage range in order to achieve energy efficiency and satisfy performance constraints as needed. Therefore, an NTC circuit may be exposed to reliability issues such as aging and voltagedrop which are significant in the superthreshold region.
In this chapter, we discussed that a nonnegligible portion of circuit flipflops may be under severe aging or large voltagedrop impact, which leads to timing and functional failures. Therefore, these flipflops need to be treated separately and specific stresstolerant designs should be used in order to improve the reliability and lifetime. Accordingly, we propose a method to selectively optimize the flipflops operating under severe aging stress and/or voltagedrop conditions. The proposed optimization flow resizes the flipflop transistors to obtain the variabilityresilient cells. Then, flipflops which are under the impact of aging and/or voltagedrop are determined using a variationaware static timing analysis tool, and are replaced by the optimized flipflops which can withstand aging and voltagedrop impacts much better. Simulation results show that the proposed selective flipflop optimization method can reduce Leon3 processor timing guardband, and improve the lifetime of the processor by 36.9%, with negligible power and area overhead.
Notes
 1.
We consider the impact of Negative Bias Temperature Instability (NBTI) on PMOS transistors, and Positive Bias Temperature Instability (PBTI) on NMOS transistors.
 2.
A C2MOS flipflop design is a master–slave flipflop built of two connected C2MOS latches. It is one of the commonly used flipflops in modern processor designs [31].
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Golanbari, M.S., Ebrahimi, M., Kiamehr, S., Tahoori, M.B. (2021). Selective FlipFlop Optimization for Circuit Reliability. In: Henkel, J., Dutt, N. (eds) Dependable Embedded Systems . Embedded Systems. Springer, Cham. https://doi.org/10.1007/9783030520175_14
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