Abstract
Reconfigurable SRAM-based Field Programmable Gate Arrays are increasingly deployed in the aerospace applications, due to their enhanced flexibility, high performance and run-time reconfiguration capabilities. The possibility to adapt on-the-fly the circuit functionality is made possible by the Internal Configuration Access Port (ICAP) that can be managed from the application through a dedicated controller. This feature enables the deployment of new optimized reconfigurable architectures for computationally intensive and fault-tolerant applications. In this context, a promising architecture is the Dynamically Reconfigurable Processing Module (DRPM), an FPGA-based modular system where the content of each reconfigurable module can be rewritten, overwritten or erased to perform performance optimization and functional modification at run-time. However, when these systems are adopted in avionic and space applications, SRAM configuration sensitivity to radiation induced soft-errors should be addressed. In this work, we evaluate the soft-error sensitivity of upsets in the configuration memory of two implementations of the ICAP controller within a DRPM system. We performed a radiation test campaign and a selective fault injection of upsets on the ICAP controller configuration memory to mimic the radiation profiles. The comparative analysis showed meaningful guidelines on the implementations of self-reconfigurable systems for the aerospace domain: the controller with distributed memory results the 28% more tolerant to low radiation environment compared to the integrated memory version, which in return results the 25% more robust considering radiation particles with higher energies.
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References
Wirthlin, M.: High-reliability FPGA-based systems: space, high-energy physics, and beyond. Proc. IEEE 103(3), 379–389 (2015)
Caffrey, M.: A space-based reconfigurable radio. In: Plaks, T.P., Athanas, P.M. (eds.) Proceedings of International Conference on Engineering of Reconfigurable Systems Algorithms, pp. 49–53. CSREA Press, Irvine, June 2002
Ferguson, R., Tate, R.: Use of field programmable gate array technology in future space avionics. In: Proceedings of 24th Digital Avionics Systems Conference (DASC 2005), vol. 2, p. 11, October/November 2005
7 Series FPGAs Configuration User Guide UG470 (v1.13.1), 20 August 2018
Sterpone, L., Porrmann, M., Hagemeyer, J.: A novel fault tolerant and runtime reconfigurable platform for satellite payload processing. IEEE Trans. Comput. 62(8), 1508–1525 (2013)
Koester, M., Luk, W., Hagemeyer, J., Porrman, M., Rueckert, U.: Design optimization for tiled partially reconfigurable systems. IEEE Trans. Very Large Scale Integr. Syst. 19(6), 1048–1061 (2011)
Quinn, H., et al.: The Cibola flight experiment. ACM Trans. Reconfig. Technol. Syst. 8, 1–22 (2014)
Dodd, P.E., Massengill, L.W.: Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans. Nucl. Sci. 50(3), 583–602 (2003)
Katz, R., et al.: Radiation effects on current field programmable technologies. IEEE Trans. Nuclear Sci. 44(6), 1945–1956 (1997)
Quinn, H.: Challenges in testing complex systems. IEEE Trans. Nucl. Sci. 61(2), 766–786 (2014)
Heiner, J., Collins, N., Wirthlin, M.: Fault tolerant ICAP controller for high-reliable internal scrubbing. In: 2008 IEEE Aerospace Conference, Big Sky, MT, pp. 1–10 (2008)
Du, B., et al.: Ultrahigh energy heavy ion test beam on Xilinx Kintex-7 SRAM-based FPGA. IEEE Trans. Nucl. Sci. 66(7), 1813–1819 (2019)
AXI HWICAP v3.0 LogiCORE IP Product Guide Vivado Design Suite PG134, 5 October 2016
AXI Reference Guide, UG761 (v13.1), 7 March 2011
Ebrahim, A., Benkrid, K., Iturbe, X., Hong, C.: A novel high-performance fault-tolerant ICAP controller. In: 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Erlangen, pp. 259–263 (2012)
Guohua, W., Dongming, L., Fengzhou, W., Adetomi, A., Arslan, T.: A tiny and multifunctional ICAP controller for dynamic partial reconfiguration system. In: 2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Pasadena, CA, pp. 71–76 (2017)
7 Series FPGAs Memory Resources User Guide UG473 (v1.14), 3 July 2019
7 Series FPGAs Configurable Logic Block User Guide UG474 (v1.8), 27 September 2016
Carmichael, C., Caffrey, M., Salazar, A.: Correcting single-event upsets through Virtex partial configuration. Xilinx Corporation, Technical report, XAPP216 (v1.0), 1 June 2000
Ceschia, M.: Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs. IEEE Trans. Nucl. Sci. 50(6), 2088–2094 (2003)
Azambuja, J.R., et al.: Evaluating neutron induced SEE in SRAM-based FPGA protected by hardware- and software-based fault tolerant techniques. IEEE Trans. Nucl. Sci. 60(6), 4243–4250 (2013)
Entrena, L., Garcia-Valderas, M., Fernandez-Cardenal, R., Lindoso, A., Portela, M., Lopez-Ongil, C.: Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injection. IEEE Trans. Comput. 61(3), 313–322 (2012)
Desogus, M., Sterpone, L., Codinachs, D.M.: Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs. In: 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), Platja d’Aro, Girona, pp. 111–115 (2014)
Sterpone, L., et al.: A novel error rate estimation approach for UltraScale+ SRAM-based FPGAs. In: 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Edinburgh, pp. 120–126 (2018)
Processing System 7 v5.5 LogiCORE IP Product Guide Vivado Design Suite PG082, 10 May 2017
Partial Reconfiguration Decoupler v1.0 LogiCORE IP Product Guide Vivado Design Suite PG227, 6 April 2016
Bozzoli, L., De Sio, C., Sterpone, L., Bernardeschi, C.: PyXEL: an integrated environment for the analysis of fault effects in SRAM-based FPGA routing. In: 2018 International Symposium on Rapid System Prototyping (RSP), Torino, Italy, pp. 70–75 (2018)
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Bozzoli, L., Sterpone, L. (2020). Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs. In: Rincón, F., Barba, J., So, H., Diniz, P., Caba, J. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2020. Lecture Notes in Computer Science(), vol 12083. Springer, Cham. https://doi.org/10.1007/978-3-030-44534-8_7
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DOI: https://doi.org/10.1007/978-3-030-44534-8_7
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