Abstract
In this chapter, we will aim to reverse the aging stress on the functional units of the processor by applying high-level workloads as anti-aging patterns into the stressed component. We present a time-redundant technique to mitigate negative and positive bias temperature instability (NBTI/PBTI) aging effects on the combinational units of a processor. We have analysed the sources and effects of aging from the device level to the instruction set architecture (ISA) level and have found that an application may stress the critical paths in such a way that the combinational circuit has half of its nodes always NBTI-stressed. To mitigate this behaviour, we propose an application-level solution to balance the stress and put the timing-critical gates of the critical path into a relaxed (balanced) mode. The results show that the lifetime of the system can be extended by applying balanced stress patterns at a higher level of abstraction and during the idle time of a processor system.
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Notes
- 1.
The technology is not important because the technique depends on reversing the SP(0) rather than estimating the aging. Hence, it is also independent of the BTI model.
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Abbas, H.M., Zwolinski, M., Halak, B. (2020). Aging Mitigation Techniques for Microprocessors Using Anti-aging Software. In: Halak, B. (eds) Ageing of Integrated Circuits. Springer, Cham. https://doi.org/10.1007/978-3-030-23781-3_3
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DOI: https://doi.org/10.1007/978-3-030-23781-3_3
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