Trends in embedded memory testing

Abstract

In recent years, embedded memories have become the fastest growing segment of system on chips (SoCs) development infrastructure. According to the International Technology Roadmap for Semiconductors (ITRS 2001), embedded memories will continue to dominate the increasing SoC content in the next years, approaching 94% in about 10 years. Further, the shrinking technology makes memories more sensitive to defects since they are among the most density package modules. Therefore the memory will have a dramatically impact on the overall defect-per-million (DPM) level, hence on the overall SoC yield; i.e., the memory yield will dominate the SoC yield. Meeting a high memory yield requires understanding memory designs, modeling their faulty behaviors in the presence of defects, designing adequate tests and diagnosis strategies as well as efficient repair schemes. This chapter presents the state of art in memory testing including fault modeling, test design, Built-In-Self-Test (BIST) and Built-In-Self-Repair (BISR). Further research challenges and opportunities are discussed in enabling testing (embedded) memories, which use deep submicron technologies.