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Testing Static Random Access Memories

Defects, Fault Models and Test Patterns

  • Said¬†Hamdioui

Part of the Frontiers in Electronic Testing book series (FRET, volume 26)

Table of contents

  1. Front Matter
    Pages i-xx
  2. Introductory

    1. Front Matter
      Pages 1-1
    2. Said Hamdioui
      Pages 3-15
    3. Said Hamdioui
      Pages 17-35
    4. Said Hamdioui
      Pages 37-64
    5. Said Hamdioui
      Pages 65-84
  3. Testing single-port and two-port SRAMs

    1. Front Matter
      Pages 85-85
    2. Said Hamdioui
      Pages 87-103
    3. Said Hamdioui
      Pages 105-134
    4. Said Hamdioui
      Pages 135-145
  4. Testing p-port SRAMs

    1. Front Matter
      Pages 147-147
    2. Said Hamdioui
      Pages 149-160
    3. Said Hamdioui
      Pages 161-174
    4. Said Hamdioui
      Pages 175-184
    5. Said Hamdioui
      Pages 185-196
  5. Back Matter
    Pages 197-221

About this book

Introduction

Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed.
Features:
-Fault primitive based analysis of memory faults,
-A complete framework of and classification memory faults,
-A systematic way to develop optimal and high quality memory test algorithms,
-A systematic way to develop test patterns for any multi-port SRAM,
-Challenges and trends in embedded memory testing.

Keywords

SRAM integrated circuit model modeling semiconductor simulation testing

Authors and affiliations

  • Said¬†Hamdioui
    • 1
  1. 1.Delft University of TechnologyThe Netherlands

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4757-6706-3
  • Copyright Information Springer-Verlag US 2004
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4419-5430-5
  • Online ISBN 978-1-4757-6706-3
  • Series Print ISSN 0929-1296
  • Buy this book on publisher's site