Our view of the language so far has been toward modeling and simulating logic hardware. We have presented language constructs that can be used to specify the intricate functionality and timing of a circuit. Using this approach, we can simulate a design using timing parameters based on circuits that have been placed and routed, giving great confidence in the results of the simulation. In this Chapter, we consider an alternate view of the language: synthesis. When using the language as an input specification for synthesis, the concern is specifying a functionally correct system while allowing a synthesis CAD tool to design the final gate level structure of the system. These views of the language are complementary. However, care must be taken in writing a description that will be used in both simulation and synthesis.
KeywordsFlip Flop Combinational Logic Clock Period Procedural Statement Synthesis Tool
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