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The Verilog® Hardware Description Language

  • Donald E. Thomas
  • Philip R. Moorby

Table of contents

  1. Front Matter
    Pages i-xix
  2. Donald E. Thomas, Philip R. Moorby
    Pages 1-32
  3. Donald E. Thomas, Philip R. Moorby
    Pages 33-64
  4. Donald E. Thomas, Philip R. Moorby
    Pages 65-96
  5. Donald E. Thomas, Philip R. Moorby
    Pages 97-140
  6. Donald E. Thomas, Philip R. Moorby
    Pages 141-168
  7. Donald E. Thomas, Philip R. Moorby
    Pages 169-197
  8. Donald E. Thomas, Philip R. Moorby
    Pages 199-211
  9. Donald E. Thomas, Philip R. Moorby
    Pages 213-244
  10. Donald E. Thomas, Philip R. Moorby
    Pages 245-254
  11. Back Matter
    Pages 255-310

About this book

Introduction

•• XVII Acknowledgments CHAPTER 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the NAND Latch 4 Module Hleral'Chy 6 The Counter 7 Components of the Counter 9 A Clock for the System 10 Tying the Whole Circuit Together 11 Using An Alternate Description of the Flip Flop 13 Behavioral Modeling 1 S A Behavioral Model of the m16 Counter 16 Mixing Structure and Behavior 18 Assignment Statements 22 Summary on Mixing Behavioral and Structural Descriptions 23 Creating a Testbench For a Module 24 Summary 2S Tutorial Guide to Formal Syntax Specification 26 Exercises 30 CHAPTER 2 Behavioral Modeling 33 Process Model 33 If-Then-Else 3S Where Does The ELSE Belong? 39 The Conditional Operator 41 Loops 41 Four Basic Loop Statements 42 Exiting Loops on Exceptional Conditions 45 Multi-way branching 46 If-Else-If 46 Case 46 Comparison of Case and If-Else-If 48 viii The Verilog Hardware Description Language Casez and Casex 49 Functions and Tasks SO Tasks 52 Functions 55 A Structural View 57 Rules of Scope and Hierarchical Names S9 Rules of Scope 60 Hierarchical Names 62 Summary 63 Exerdses 63 CHAPTER 3 Concurrent Processes 6S Concu"ent Processes 6S Events 67 Event Control Statement 67 Named Events 69 The Walt Statement 72 A Complete Producer-Consumer Handshake 74 Comparison of the Wait and While Statements 77 Comparison of Wait and Event Control Statements 78 A Concu"ent Process Example 78 Disabling Named Blocks 84 Intra-Assignment Control and Timing Events 87 Procedural Continuous Assignment 90

Keywords

Advanced VLSI Describing digital systems Formal verification Hardware Logic design and simulation Simulating digital systems Synthesizing digital systems Thomas and Moorby Verification Verilog model modeling

Authors and affiliations

  • Donald E. Thomas
    • 1
  • Philip R. Moorby
    • 2
  1. 1.Carnegie Mellon UniversityUSA
  2. 2.Avid Technology, Inc.USA

Bibliographic information