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Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

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High Performance Clock Distribution Networks

Abstract

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semiconductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits.

This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared.

In many circuit topologies of current medium to large scale RSFQ circuits, single-phase synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Synchronous clocking of RSFQ circuits at multigigahertz frequencies requires the application of non-standard design techniques such as pipelined clocking and intentional non-zero clock skew. Even with these techniques, there exist difficulties which arise from the deleterious effects of process variations on circuit yield and performance. As a result, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes.

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References

  1. K.K. Likharev and V.K. Semenov, “RSFQ logic/memory family: A new Josephson junction technology for sub-terahertzclock frequency digital systems,” IEEE Trans. Appl. Supercond., Vol. 1, pp. 3–28, 1991.

    Article  Google Scholar 

  2. K.K. Likharev, “Rapid single-flux-quantum logic,” in The New Superconductor Electronics, H. Weinstock and R. Ralston (Eds.), Kluwer, Dordrecht, pp. 423–452, 1993.

    Google Scholar 

  3. O.A. Mukhanov, P.D. Bradley, S.B. Kaplan, S.V. Rylov, and A.F. Kirichenko, “Design and operation of RSFQ circuits for digital signal processing,” Proc. 5th Int. Supercond. Electron. Conf:, Nagoya, Japan, Sept. 1995, pp. 27–30.

    Google Scholar 

  4. K.K. Likharev, “Ultrafast superconcductor digital electronics: RSFQ technology roadmap,” Czechoslovak J. Phys., Suppl. S6, Vol. 46, 1996.

    Google Scholar 

  5. O.A. Mukhanov and A.F. Kirichenko, “Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 2461–2464, 1995.

    Article  Google Scholar 

  6. J.C. Lin, V.K. Semenov, and K.K. Likharev, “Design of SFQcounting analog-to-digital converter,” IEEE Trans. App!. Supercond., Vol. 5, pp. 2252–2259, 1995.

    Article  Google Scholar 

  7. V.K. Semenov, Yu. Polyakov, and D. Schneider, “Preliminary results on the analog-to-digital converter based on RSFQ logic.” CPEM96 Conf. Digest Suppl., Braunschweig, Germany, June 1996, pp. 15–16.

    Google Scholar 

  8. Q.P. Herr et al. “Design and low speed testing of a four-bit RSFQ multiplier-accumulator,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  9. Q.P. Herr, K. Gaj, A.M. Herr, N. Vukovic, C.A. Mancini, M.F. Bocko, and M.J. Feldman, “High speed testing of a four-bit RSFQ decimation digital filter,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  10. P.I. Bunyk et al., “High-speed single-flux-quantum circuit using planarized niobium-trilayer Josephson junction technology,” Appl. Phys. Lett., Vol. 66, pp. 646–648, 1995.

    Article  Google Scholar 

  11. Q.P. Herr and M.J. Feldman, “Error rate of a superconducting circuit,” Appl. Phys. Len., Vol. 69, pp. 694–695, 1996.

    Article  Google Scholar 

  12. D.Y. Zinoviev and K.K. Likharev, “Feasibility study of RSFQbased self-routing nonblocking digital switches,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  13. Q. Ke, B.J. Dalrymple, D.J. Durand, and J.W. Spargo, “Single flux quantum crossbar switch,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  14. N.B. Dubash, P-F. Yuh, V.V. Borzenets, T. Van Duzer, and S.R. Whiteley, “SFQ data communication switch,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  15. O.A. Mukhanov and S.V. Rylov, “Time-to-digital converters based on RSFQ digital counters,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  16. A.V. Rylyakov and S.V. Polonsky, “All digital 1-bit RSFQ autocorrelator for radioastronomy applications: Design and experimental results,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  17. A.V. Rylyakov, “New design of single-bit all-digital RSFQ autocorrelator,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  18. G. Taubes, “Redefining the supercomputer,” Science, Vol. 273, pp. 1655–1657, 1996.

    Article  Google Scholar 

  19. G. Gao, K.K. Likharev, P.C. Messina, and T.L. Sterling, “Hybrid technology multithreaded architecture,” in Proc of PetaFlops Architecture Workshop,to be published; see also the Web site http://www.cesdis.gsfc.nasa.gov/petaflops/peta.html.

    Google Scholar 

  20. C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, Reading, MA, 1980.

    Google Scholar 

  21. M. Hatamian, “Chapter 6, Understanding clock skew in synchronous systems,” in Concurrent Computations (Algorithms, Architecture, and Technology), S.K. Tewksbury, B.W. Dickinson, and S.C. Schwartz (Eds.), Plenum Publishing, New York, pp. 87–96, 1988.

    Google Scholar 

  22. H.B. Bakoglu, Circuits, Interconnections and Packaging, for VLSI, Addison-Wesley, 1990.

    Google Scholar 

  23. H.M. Teresa, Synchronization Design for Digital Systems, Kluwer Academic Publishers, 1991.

    Google Scholar 

  24. E.G. Friedman, “Clock distribution design in VLSI circuits—an overview,” Proc. IEEE Int’l Symp. Circuits Syst., pp. 1475–1478, May 1993.

    Google Scholar 

  25. E.G. Friedman (Ed.), Clock Distribution Networks in VLSI Circuits and Systems, IEEE Press, 1995.

    Google Scholar 

  26. O.A. Mukhanov, S.V. Rylov, V.K. Semenov, and S.V. Vyshenskii, “RSFQ logic arithmetic, ” IEEE Trans. Magnetics, Vol. 25, pp. 857–860, 1989.

    Article  Google Scholar 

  27. K. Gaj, E.G. Friedman, M.J. Feldman, and A. Krasniewski, “A clock distribution scheme for large RSFQ circuits,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 3320–3324, 1995.

    Article  Google Scholar 

  28. A.L. Fisher and H.T. Kung, “Synchronizing large VLSI processor arrays,” IEEE Trans. Comput., Vol. C-34, pp. 734–740, 1985.

    Google Scholar 

  29. M. Afghahi and C. Svensson, “Performance of synchronous and asynchronous schemes for VLSI systems,” IEEE Trans. Comput., Vol. C-41, pp. 858–872, 1992.

    Google Scholar 

  30. K. Gaj, C.-H. Cheah, E.G. Friedman, and M.J. Feldman, “Optimal clocking design for large RSFQ circuits using Verilog HDL,” (in preparation).

    Google Scholar 

  31. J.P. Fishburn, “Clock skew optimization,” IEEE Trans. Comput., Vol. 39, pp. 945–951, 1990.

    Article  Google Scholar 

  32. J.L. Neves and E.G. Friedman, “Topological design of clock distribution networks based on non-zero clock skew,” Proc. 36th Midwest Symp. Circuits Syst., pp. 468–471, Aug. 1993.

    Google Scholar 

  33. J.L. Neves and E.G. Friedman, “Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew,” IEEE Trans. VLSI Syst., Vol. 4, pp. 286–291, 1996.

    Article  Google Scholar 

  34. J.L. Neves and E.G. Friedman, “Circuit synthesis of clock distribution networks based on non-zero clock skew,” Proc. IEEE Intl Symp. Circuits Syst., pp. 4. 175–4. 178, June 1994.

    Google Scholar 

  35. J.L. Neves and E.G. Friedman, “Automated synthesis of skew-based clock distribution networks,” Int’l J. VLSI Design, March 1997.

    Google Scholar 

  36. S.Y. Kung and R.J. Gal-Ezer, “Synchronous versus asynchronous computation in very large scale integrated (VLSI) array processors,” Proc. of SPIE, Vol. 341, pp. 53–65, May 1982.

    Google Scholar 

  37. I.E. Sutherland, “Micropipelines,” Comm. ACM, Vol. 32, pp. 720–738, 1989.

    Article  Google Scholar 

  38. Z.J. Deng, S.R. Whiteley, and T. Van Duzer, “Data-driven self-timing of RSFQ digital integrated circuits,” ext. abstract, 5th Int’l Supercond. Electr. Cont. (ISEC), Nagoya, Sept. 1995, pp. 189–191.

    Google Scholar 

  39. M. Maezawa, I. Kurosawa, Y. Kameda, and T. Nanya, “Pulse-driven dual-rail logic gate family based on rapid single-fluxquantum (RSFQ) devices for asynchronous circuits,” Proc. 2nd Int. Symposium Advanced Research in Asynchronous Circuits and Systems, pp. 134–142, March 1996.

    Google Scholar 

  40. M. Hatamian and G.L. Cash, “Parallel bit-level pipelined VLSI design for high-speed signal processing,” Proc. IEEE, Vol. 75, pp. 1192–1202, Sept. 1987.

    Article  Google Scholar 

  41. D.C. Wong, G.D. Micheli, and M.J. Flynn, “Designing of high-performance digital circuits using wave pipelining: Algorithms and practical experiences,” IEEE Trans. Comp. Aid. Design Int. Circ. and Syst., Vol. 12, pp. 25–46, 1993.

    Article  Google Scholar 

  42. D.A. Joy and M.J. Ciesielski, “Clock period minimization with wave pipelining,” IEEE Trans. Comp.-Aid. Design Im’. Circ. and Syst., Vol. 12, pp. 461–472, 1993.

    Article  Google Scholar 

  43. Q. Ke and M.J. Feldman, “Single flux quantum circuits using the residue number system,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 2988–2991, 1995.

    Article  Google Scholar 

  44. Q. Ke, “Superconducting single flux quantum circuits using the residue number system,” Ph.D. Thesis, University of Rochester, 1995.

    Google Scholar 

  45. K.K. Likharev, O.A. Mukhanov, and V.K. Semenov, “Resistive single flux quantum logic for the Josephson-junction technology,” in SQUID’85, Berlin, Germany, W. de Gruyter, pp. 11031108, 1985.

    Google Scholar 

  46. S.V. Polonsky, V.K. Semenov, and D.F. Schneider, “Transmission of single-flux-quantum pulses along superconducting microstrip lines,” IEEE Trans. Appl. Supercond., Vol. 3, pp. 25982600, 1993.

    Google Scholar 

  47. S.V. Polonsky et al., “New RSFQ circuits,” IEEE Trans. Appl. Supercond., Vol. 3, pp. 2566–2577, 1993.

    Article  Google Scholar 

  48. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design—A Systems Perspective, Addison-Wesley, Reading, MA, 1985.

    Google Scholar 

  49. S.B. Kaplan and O.A. Mukhanov, “Operation of a superconductive demultiplexer using rapid single flux quantum (RSFQ) technology,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 28532856, 1995.

    Google Scholar 

  50. A.F. Kirichenko, V.K. Semenov, Y.K. Kwong, and V. Nandakumar, “4-bit rapid single-flux-quantum decoder,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 2857–2860, 1995.

    Article  Google Scholar 

  51. S.V. Polonsky, V.K. Semenov, and A.F. Kirichenko, “Single flux, quantum B flip-flop and its possible applications,” IEEE Trans. Appl. Supercond., Vol. 4, pp. 9–18, 1994.

    Article  Google Scholar 

  52. S.S. Martinet and M.F. Bocko, “Simulation and optimization of binary full-adder cells in RSFQ logic,” IEEE Trans. Appl. Supercond., Vol. 3, pp. 2720–2723, 1993.

    Article  Google Scholar 

  53. A.F. Kirichenko and O.A. Mukhanov, “Implementation of novel `push-forward’ RSFQ carry-save serial adders,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 3010–3013, 1995.

    Article  Google Scholar 

  54. S.V. Polonsky, J.C. Lin, and A.V. Rylyakov, “RSFQ arithmetic blocks for DSP applications,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 2823–2826, 1995.

    Article  Google Scholar 

  55. Z.J. Deng, N. Yoshikawa, S.R. Whiteley, and T. Van Duzer, “Data-driven self-timed RSFQ digital integrated circuit and system,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  56. I. Kurosawa, H. Nakagawa, M. Aoyagi, M. Maezawa, Y. Kameda, and T. Nanya, “A basic circuit for asynchronous superconductive logic using RSFQ gates,” in Extended Abstracts of 5th Int’l Supercond. Electr. Conf: (ISEC), Nagoya, Sept. 1995, pp. 204–206.

    Google Scholar 

  57. I. Kurosawa, H. Nakagawa, M. Aoyagi, M. Maezawa, Y. Kameda, and T. Nanya, “A basic circuit for asynchronous superconductive logic using RSFQ gates,” Supercond. Sci. Technol., Vol. 8, pp. A46 — A49, 1995.

    Google Scholar 

  58. M. Maezawa, I. Kurosawa, M. Aoyagi, H. Nakagawa, Y. Kameda, and T. Nanya, “Rapid single-flux-quantum dual-rail logic for asynchronous circuits,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  59. C.A. Mancini, N. Vukovic, A.M. Herr, K. Gaj, M.F. Bocko, and M.J. Feldman, “RSFQ circular shift registers,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  60. P. Bunyk and A. Kidiyarova-Shevchenko, “RSFQ microprocessor: New design approaches,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  61. P. Bunyk and V.K. Semenov, “Design of an RSFQ microprocessor,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 3325–3328, 1995.

    Article  Google Scholar 

  62. P. Patra and D.S. Fussell, “Conservative delay-insensitive circuits,” Proc. 4th Workshop on Physics and Computation: PhysComp96, Boston, 1996, pp. 248–259.

    Google Scholar 

  63. J. Fleischman and T. Van Duzer, “Computer architecture issues in superconductive microprocessors,” IEEE Trans. Appl. Supercond., Vol. 3, pp. 2716–2719, 1993.

    Article  Google Scholar 

  64. V.K. Kaplunenko, “Fluxon interaction in an overdamped Josephson transmission line,” Appl. Phys. Lett., Vol. 66, pp. 3365–3367, 1995.

    Article  Google Scholar 

  65. J.-C. Lin and V.K. Semenov, “Timing circuits for RSFQ digital systems,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 3472–3477, June 1995.

    Article  Google Scholar 

  66. A. Yu. Kidiyarova-Shevchenko and D. Yu. Zinoviev, “RSFQ pseudo-random generator and its possible applications,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 2820–2822, 1995.

    Article  Google Scholar 

  67. H.B. Bakoglu, J.T. Walker, and J.D. Meindl, “A symmetric clock-distribution tree and optimized high-speed interconnections for reduced clock skew in VLSI and WSI circuits,” IEEE Int’l Conf Computer Design, pp. 118–122, Oct. 1986.

    Google Scholar 

  68. M. Shoji, `Elimination of process-dependent clock skew in CMOS VLSI,“ J. Solid- State Circuits, Vol. SC-2I, pp. 875880, 1986.

    Google Scholar 

  69. D.C. Keezer, “Design and verification of clock distribution in VLSI,” Proc. IEEE Int’l Conf Commun. ICC’90, Vol. 3, pp. 317.7.1–317. 7. 6, April 1990.

    Google Scholar 

  70. M.D. Dikaiakos and K. Steiglitz, “Comparison of tree and straight-line clocking for long systolic arrays,” J. VLSI Signal Processing, Vol. 3, pp. 1177–1180, 1991.

    Google Scholar 

  71. Hypres niobium process flow and design rules,“ Available from Hypres, Inc., 175 Clearbrook Road, Elmsford, NY 10523.

    Google Scholar 

  72. TRW topological design rule for Josephson junction technology JJ-110A,“ available from TRW, One Space Park, Redondo Beach, CA 90278.

    Google Scholar 

  73. Z. Bao, M. Bhushan, S. Han, and J.E. Lukens, “Fabrication of high quality, deep-submicron Nb/A1Ox/Nb Josephson junctions using chemical mechanical polishing,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 2731–2734, 1995.

    Article  Google Scholar 

  74. K. Gaj, Q.P. Herr, and M.J. Feldman, “Parameter variations and synchronization of RSFQ circuits,” Applied Superconductivity 1995, Institute of Physics Conf. Series #148, Bristol, UK, 1995, pp. 1733–1736.

    Google Scholar 

  75. A.D. Smith, S.L. Thomasson, and C. Dang, “Reproducibility of niobium junction critical currents: Statistical analysis and data,” IEEE Trans. Appl. Supercond., Vol. 3, pp. 2174–2177, 1993.

    Article  Google Scholar 

  76. Q.P. Herr and M.J. Feldman, “Multiparameter optimization of RSFQ circuts using the method of inscribed hyperspheres,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 3337–3340, June 1995.

    Article  Google Scholar 

  77. L.A. Abelson, K. Daly, N. Martinez, and A.D. Smith, “LTS Josephson junction critical current uniformities for LSI applications,” IEEE Trans. Appl. Supercond., Vol. 5, pp. 2727–2730, 1995.

    Article  Google Scholar 

  78. S.D. Kugelmass and K. Steiglitz, “An upper bound of expected clock skew in synchronous systems,” IEEE Trans. Comput., Vol. 39, pp. 1475–1477, 1990.

    Article  Google Scholar 

  79. K. Gaj, C.-H. Cheah, E.G. Friedman, and M.J. Feldman, “Functional modeling of RSFQ circuits using Verilog HDL,” IEEE Trans. Appl. Supercond., Vol. 7, 1997.

    Google Scholar 

  80. R.-F. Yuh, “Shift registers and correlators using a two-phase single flux quantum pulse clock,” IEEE Trans. Appl. Supercond., Vol. 3, pp. 3009–3012, 1993.

    Article  Google Scholar 

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  1. Department of Electrical Engineering, University of Rochester, Rochester, New York, 14627, USA

    Kris Gaj, Eby G. Friedman & Marc J. Feldman

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  1. University of Rochester, USA

    Eby G. Friedman

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Gaj, K., Friedman, E.G., Feldman, M.J. (1997). Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits. In: Friedman, E.G. (eds) High Performance Clock Distribution Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-8440-3_11

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  • DOI: https://doi.org/10.1007/978-1-4684-8440-3_11

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