Abstract
Satellite and avionics applications represent an ideal application for the tremendous performance, cost, space, and reliability benefits of MCMs. These advantages are only realized, however, if accompanied by an efficient test strategy which verifies defect-free fabrication. This paper describes a methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multi-chip silicon substrate. A test strategy, which addresses testing from the wafer level through to the populated substrate, is detailed. This strategy uses a combination of LSSD, AC LSSD-On-Chip Self Test, Deterministic Delay Fault Testing, and Design for Partitionability to ensure high test quality at a reasonable cost. The methodology is then contrasted to alternative approaches.
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References
N.F. Haddad, W.B. Henley, and C. Schlier, “A Radiation Hardened Half Micron Technology,” Government Microcircuit Applications Conference Digest, Nov. 1988.
F.D. Austin, D.C. Green, and M.A. Robbins, “VCOS (VH-SIC Chips-on-Silicon): Packaging, Performance, and Applications,” Government Microcircuit Applications Conference Digest, Nov. 1990, pp. 577–581.
R.C. Frye, K.L. Tai, M.Y. Lau, and T.J. Gabara, “Trends in Silicon on Silicon Multichip Modules,” IEEE Design and Test of Computers, Vol. 10, No. 4, pp. 8–17, Dec. 1993.
J.J. LeBlanc, “LOCST: A Built-in Self-Test Technique,” IEEE Design and Test of Computers, Vol. 1, pp. 45–42, March 1984.
R.H. Bardell, W.H. McAnney, and J. Savir, Built-in Test for VLSI: Pseudorandom Techniques, John Wiley & Sons Inc., New York, 1987.
P.S. Bottorff, R.E. France, N.H. Garges, and E.J. Orosz, “Test Generation for Large Logic Networks,” Proc. Design Automation Conference, June 1977, pp. 479–485.
T. Storey, W. Maly, J. Andrews, and M. Miske, “Stuck Fault and Current Testing Comparison using CMOS Chip Test,” Proc. International Test Conference, Oct. 1991.
R.K. Gulati and C.F. Hawkins, I DDQ Testing of VLSI Circuits, Kluwer Academic Publishers, Boston, 1993.
R. Rajsuman, IDDQ Testing for CMOS VLSI, Artech House, 1995.
F. Motika, N.N. Tendolkar, C.C. Beh, W.R. Heller, C.E. Radke, and P.J. Nigh, “A Logic Chip Delay Test Method Based on System Timing,” IBM Journal of Research and Development, Vol. 34, pp. 299–313, March/May 1990.
B.L. Keller and T.J. Snethen, “Built-in Self-Test Support in the IBM Engineering Design System,” IBM Journal of Research & Development, Vol. 34, pp. 406–415, March/May 1990.
K.-T. Cheng and C.J. Lin, “Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST,” Proc. International Test Conference, Oct. 1995, pp. 506–514.
B. Koenemann, “LFSR-Coded Test Patterns for Scan Designs,” Proc. European Test Conference, April 1991, pp. 237–242.
N.A. Touba and E.J. McCluskey, “Altering a Pseudo-Random Bit Sequence for Scan-Based BIST,” Proc. International Test Conference, Oct. 1996, pp. 167–175.
E.P. Hsieh, R.A. Rasmussen, L.J. Vidunas, and W.T. Davis, “Delay Test Generation,” Proc. Design Automation Conference, June 1977, pp. 486–491.
T. Storey and J. Barry, “Delay Fault Simulation,” Proc. Design Automation Conference, June 1977, pp. 492–494.
W.K. Lam, A. Saldanha, R.K. Brayton, and A.L. Sangiovanni-Vicentelli, “Delay Fault Coverage, Test Set Size, and Performance Trade-Offs,” IEEE Trans. on CAD, Vol. 14, No. 1, pp. 32–44, Jan. 1995.
K.-T. Cheng and H.-C. Chen, “Generation of High Quality Non-Robust Tests for Path Delay Faults,” Proc. Design Automation Conf., June 1994, pp. 365–369.
J.A. Waicukauski, E. Lindbloom, B.K. Rosen, and V.S. Iyengar, “Transition Fault Simulation by Parallel Pattern Single Fault Propagation,” International Test Conference, Sept. 1986, pp. 543–549.
Y. Levendel and P.R. Menon, “Transition Faults in Combinational Circuits: Input Transition Test Generation and Fault Simulation,” Fault-Tolerant Computing Systems, pp. 278–273, July 1986.
B. Koeneman et al., “Delay Test: The Next Frontier for LSSD Test Systems,” Proc. International Test Conference, Sept. 1992, pp. 578–587.
P.H. Bardell and W.H. McAnney, “Self-Testing of Multichip Logic Modules,” Proc. International Test Conference, Sept. 1982, pp. 200–204.
D.P. Seraphim and I. Feinberg, “Electronic Packaging Evolution in IBM,” IBM Journal of Research and Development, Vol. 25, No. 5, pp. 617–629, Sept. 1981.
IEEE Standard 1149.1-1993a, “IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE, New York, NY, Oct. 1993.
K.P. Parker, The Boundary-Scan Handbook, Kluwer Academic Publishers, p. 52, 1992.
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Storey, T.M., McWilliam, B., Zorian, Y. (1997). A Test Methodology for High Performance MCMs. In: Zorian, Y. (eds) Multi-Chip Module Test Strategies. Frontiers in Electronic Testing, vol 7. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6107-1_10
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DOI: https://doi.org/10.1007/978-1-4615-6107-1_10
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