Abstract
In this chapter, the ESD resistance of a given MOS technology is analyzed in terms of the ESD performance of the most commonly used protection structure, namely the nMOS device itself. Section 2.1 gives an overview of ESD physical phenomena in the nMOS device and the design criteria for ESD protection devices. Section 2.2 reviews the failure modes in nMOS ESD protection devices. Sections 2.3 and 2.4 describe ESD nMOS protection schemes and the impact that advanced processing techniques such as LDD and silicidation have on the nMOS ESD robustness. Finally, Section 2.5 discusses protection concepts for advanced MOS technologies.
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© 1995 Springer Science+Business Media New York
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Díaz, C.H., Kang, SM., Duvvury, C. (1995). NMOS ESD Protection Devices and Process Related Issues. In: Modeling of Electrical Overstress in Integrated Circuits. The Springer International Series in Engineering and Computer Science, vol 289. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2788-6_2
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DOI: https://doi.org/10.1007/978-1-4615-2788-6_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6205-0
Online ISBN: 978-1-4615-2788-6
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