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Modeling of Electrical Overstress in Integrated Circuits

  • Carlos H. Díaz
  • Sung-Mo Kang
  • Charvaka Duvvury

Table of contents

  1. Front Matter
    Pages i-xxv
  2. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
    Pages 1-10
  3. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
    Pages 11-24
  4. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
    Pages 25-42
  5. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
    Pages 43-61
  6. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
    Pages 63-71
  7. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
    Pages 73-83
  8. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
    Pages 85-110
  9. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
    Pages 111-128
  10. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
    Pages 129-132
  11. Back Matter
    Pages 133-148

About this book

Introduction

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits.
The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure.
Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields.

Keywords

VLSI development integrated circuit material modeling semiconductor semiconductor devices simulation tables testing

Authors and affiliations

  • Carlos H. Díaz
    • 1
  • Sung-Mo Kang
    • 2
  • Charvaka Duvvury
    • 3
  1. 1.Integrated Circuits Business Division, R&D CenterHewlett-Packard CompanyPalo AltoUSA
  2. 2.Coordinated Science LaboratoryUniversity of IllinoisUrbanaUSA
  3. 3.Semiconductor Process and Design CenterTexas Instruments IncorporatedDallasUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-2788-6
  • Copyright Information Kluwer Academic Publishers 1995
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-6205-0
  • Online ISBN 978-1-4615-2788-6
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site