Skip to main content

Area Array Component Replacement Technology

  • Chapter
Area Array Interconnection Handbook
  • 847 Accesses

Abstract

As surface mount technology advanced from peripheral-leaded to area-array (AA) devices, assembly shops benefited from significant improvements in process yields and component reliability.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. W. Nelson, Applied Life Data Analysis, New York: John Wiley & Sons, 1982, pp. 84–91, 200–204.

    Book  MATH  Google Scholar 

  2. P. McCallum, private communication, Apr. 1998.

    Google Scholar 

  3. M. Fine and D. Jeannotte, “Soft Solder-General Principles and Fatigue Lifetime Estimation,” Proc. Microelectronic Packaging Technology Materials and Processes, (Philadelphia, Pennsylvania), pp. 147–158, Apr. 1989.

    Google Scholar 

  4. S. Fauzer, C. Ramirez and L. Hollinger, “High Pin-Count PBGA Assembly,” Circuits Assembly, pp. 36–40, Feb. 1995.

    Google Scholar 

  5. D. Best and S. Singfiel, private communication, 1991.

    Google Scholar 

  6. EIA/JEDEC Test Method A112-A, Moisture-Induced Stress Sensitivity for Plastic Surface Mount Devices, Nov. 1995.

    Google Scholar 

  7. M. Economou, S. Sato, G. Vial-David and L. Repellin, “The Challenges of Area Array Rework,” Proc. Nepcon West, (Anaheim, California), pp. 1633–1645, Feb. 26-Mar. 2, 1995.

    Google Scholar 

  8. D. J. Becker, J. Bielick and M. Swain, “Heatsink Removal Tool,” IBM Technical Disclosure Bulletin, vol. 38 (2), Feb. 1995, pp. 173–174.

    Google Scholar 

  9. C. S. Chang, “Printed Circuit Board Signal Line Electrical Design,” Principles of Electronic Packaging, D. P. Seraphim, R. C. Lasky and C. Y. Li, eds., New York: McGraw-Hill Book Co., 1989, pp. 110–112.

    Google Scholar 

  10. B. Czaplicki, “Effective Rework of BGA Devices,” Australian Electronics Engineering vol. 28(3), pp. 34–35, Mar. 1995.

    Google Scholar 

  11. J. Bielick, unpublished.

    Google Scholar 

  12. D. Best, J. Bielick, P. Isaacs and J. Stephanie, “High Glass Transition Temperature Laminates: Impact on BGA Rework,” Proc. Nepcon West, (Anaheim, California), pp. 906–921, Feb. 1996.

    Google Scholar 

  13. J. Nash, G. Knotts and P. Isaacs, unpublished.

    Google Scholar 

  14. C. G. Woychik and R. C. Senger, “Joining Materials and Processes in Electronic Packaging,” Principles of Electronic Packaging, D. P. Seraphim, R. C. Lasky and C. Y. Li, eds., New York: McGraw-Hill Book Co., 1989, pp. 588–590.

    Google Scholar 

  15. R. J. Klein Wassink, Soldering in Electronics, Ayr, Scotland: Electrochemical Publications Limited, 1984, pp. 93–108.

    Google Scholar 

  16. S. V. Vasan, P. T. Truong and G. Dody, “Flipchip Rework Process,” Proc. Surface Mount Int., (San Jose, California), pp. 225–231, Aug. 28—Sept. 1, 1994.

    Google Scholar 

  17. E. Zamborsky, “BGAs in the Assembly Process,” Circuits Assembly, vol. 7 (5) pp. 68–70, May 1996.

    Google Scholar 

  18. C. G. Heim, R. H. Lewis, M. V. Pierson, K. J. Puttlitz, “Method for Restraining Circuit Board Warp During Area Array Rework,” U.S. Patent 5,862,588, 1999.

    Google Scholar 

  19. C. Milkovich, private communication.

    Google Scholar 

  20. M. G. Pecht and L. T. Nguyen, “Plastic Packaging,” Microelectronics Packaging Handbook Vol. II, R. R. Tummala, E. J. Rymaszewski and A. G. Klopfenstein, eds., New York: Chapman & Hall, 1997, p. 464.

    Google Scholar 

  21. G. Huston, P. Isaacs, G. Knotts and M. Swain, “Surface Mount Micro-Screener,” IBM Technical Disclosure Bulletin, vol. 37(11) Nov. 1994, pp. 271–274.

    Google Scholar 

  22. P. Isaacs, R. Lewis and M. Swain, “Ball Grid Array and Column Grid Array Module Solder Stencil Template,” IBM Technical Disclosure Bulletin, vol. 37 (6B), June 1994, pp. 225–226.

    Google Scholar 

  23. P. Isaacs, R. Lewis and M. Swain, “Ball Grid Array and Column Grid Array Module Solder Paste Fixtures/Handlers,” IBM Technical Disclosure Bulletin, vol. 37, (06B), June 1994, pp. 363–366.

    Google Scholar 

  24. P. Wang and K. Takasu, “Machine Accuracy Assessment for Advanced Package Placement,” Proc. Nepcon West, (Anaheim, California), pp. 87–99, Feb. 1999.

    Google Scholar 

  25. H. Lowe and R. Lyn, “Real World Flip Chip Assembly: A Manufacturer’s Experience,” Proc. Surface Mount Int., (San Jose, California), pp. 80–87, Aug. 29–31, 1995.

    Google Scholar 

  26. G. Odian, Principles of Polymerization, New York: John Wiley & Sons, Inc., 1991, 3rd edition, pp. 134–136.

    Google Scholar 

  27. J. Stephanie and J. Kuczynski, “Reworkable Globtop Encapsulation,” Proc. Nepcon West, (Anaheim, California), pp. 366–379, Feb. 23–25,1997.

    Google Scholar 

  28. S. L. Buchwalter, J. P. Kuczynski and J. G. Stephanie, “Cleavable Diepoxides For Removable Epoxy Compositions,” U.S. Patent 5,932,682,1999.

    Google Scholar 

  29. P. Elenius, “Technology Options for Flip Chip Bumping and Assembly,” Proc. Pan Pacific Microelectronics Symposium, (Maui, Hawaii), pp. 453–459, Jan. 28–31,1997.

    Google Scholar 

  30. R. Venkatraman, M. Jimarez and K. Fallon, “Decal Solder Bumping Process for Direct Flip Chip Attach Applications,” Proc. International Symposium on Flip Chip, TAB and Ball Grid Array Technology, (San Jose, California), pp. 88–95, Feb. 14–17, 1995.

    Google Scholar 

  31. R. Godin, S. Pearson and R. Lasky, “A Novel Process for Solder Deposition,” Surface Mount Technology, Special Series: Partners in Manufacturing, pp. 66–68, Jan. 1997.

    Google Scholar 

  32. T. Schiesser, E. Menard, T. Smith and J. Akin, “Microdynamic Solder Pump vs Alternatives: Comparative Review of Solder Bumping Techniques for Flip Chip Attach,” Proc. Surface Mount Int., (San Jose, California), pp. 171–178, Aug. 29–31, 1995.

    Google Scholar 

  33. D. J. Peck, “MicroBGA Processing and Rework,” Proc. Nepcon West, (Anaheim, California), pp. 63–72, Feb. 1999.

    Google Scholar 

  34. R. Lee, J. Liao, I. Tzeng and J. Lin, “Development of Fine Pitch Screen Printing Technology Through Design of Experiment,” Proc. Pan Pacific Microelectronics Symposium, (Maui, Hawaii), pp. 453–459, Jan. 28–31, 1997.

    Google Scholar 

  35. W. E. Coleman, “Stencil Design for Advanced Packages,” Surface Mount Technology, June 1996.

    Google Scholar 

  36. S. F. Kench, “Rework Process for Chip Scale Components,” Proc. Surface Mount Int., (San Jose, California), pp. 260–265, Sept. 10–12, 1996.

    Google Scholar 

  37. S. Fauzer, C. Ramirez and L. Hollinger, “High Pin Count PBGA Assembly: Solder Defect Failure Modes and Root Cause Analysis,” Proc. Surface Mount Int., (San Jose, California), pp. 169–174, Aug. 28-Sept. 1, 1994.

    Google Scholar 

  38. S. Thomas and C. Thornton, “BGA Process Development and SPC Implementation Using In line X-Ray Laminography Measurements,” Proc. Surface Mount Int., (San Jose, California), pp. 367–372, Aug. 29–31, 1995.

    Google Scholar 

  39. J. Laatikainen and P. Kess, “X-ray Inspection Helps Improve Process Yield,” Circuits Assembly, vol. 8 (3), pp. 38–45, Mar. 1997.

    Google Scholar 

  40. A. J. Downing, D. C. Foster and K. J. Puttlitz, “Apparatus and Method for Removing Meltable Material from a Substrate,” U.S. Patent 5,620,132,1997.

    Google Scholar 

  41. R. Samos and M. Denlinger, “Boosting BGA Yield,” Advanced Packaging’s Guide to Emerging Technologies, pp. 15–16, Jul./Aug. 1997.

    Google Scholar 

  42. D. Baska and P. Isaacs, unpublished work.

    Google Scholar 

  43. P. Isaacs, unpublished work.

    Google Scholar 

  44. E. M. Ingalls, M. S. Cole, J. Jozwiak, C. Milkovich and J. Stack, “Improvement in Reliability with CCGA Column Density Increase to 1-mm Pitch,” Proceedings of the 48th Electronics Components and Technology Conference, (Seattle, Washington), pp. 1298–1304, May 1998.

    Google Scholar 

  45. R. Gibbs, “Rework System Selection,” Circuits Assembly, vol. 7(5), pp. 40–42, May 1996.

    Google Scholar 

  46. R. Bonnell, private communication.

    Google Scholar 

  47. E. Zamborsky, “BGA Rework System,” Circuits Assembly, Dec. 1995.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Karl J. Puttlitz Paul A. Totta

Rights and permissions

Reprints and permissions

Copyright information

© 2001 Springer Science+Business Media New York

About this chapter

Cite this chapter

Isaacs, P., Puttlitz, K.J. (2001). Area Array Component Replacement Technology. In: Puttlitz, K.J., Totta, P.A. (eds) Area Array Interconnection Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1389-6_20

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-1389-6_20

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5529-8

  • Online ISBN: 978-1-4615-1389-6

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics