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Area Array Interconnection Handbook

  • Editors
  • Karl J. Puttlitz
  • Paul A. Totta

Table of contents

  1. Front Matter
    Pages i-lxviii
  2. History of Flip Chip and Area Array Technology

  3. Chip-Level Technology

    1. Front Matter
      Pages 37-37
    2. Paul Totta, Glenn Rinne, Peter Elenius, Michael Varnau, Thomas Oppert, Elke Zakel et al.
      Pages 39-116
    3. Gobinda Das, Franco Motika, Eugene Atwood
      Pages 117-148
    4. Claude L. Bertin, Lo-Soun Su, Jody Van Horn
      Pages 149-200
    5. Lyman R. Clark, Mark Brown, Scott Evans, Steve Bedore, Charles E. Gutentag, Robert A. Sierra
      Pages 201-227
    6. John U. Knickerbocker, Thomas F. Redmond
      Pages 228-267
    7. Happy T. Holden, Donald Barr, Douglas Powell
      Pages 268-314
    8. Peter J. Brofman, Karl J. Puttlitz, Kathleen A. Stalter, Charles Woychik
      Pages 315-349
    9. Karl J. Puttlitz, Kathleen A. Stalter
      Pages 350-370
    10. David L. Edwards, Barrie C. Campbell, James H. Covell II, Kenneth C. Marston, Camille Proietti-Bowne
      Pages 371-420
    11. Eugene Atwood, Glenn Daves
      Pages 421-451
    12. Stephen L. Buchwalter, Maurice E. Edwards, Daniel Gamota, Michael A. Gaynes, Son K. Tran
      Pages 452-499
    13. Giulio DiGiacomo, Jasvir S. Jaspal
      Pages 500-548
  4. Package-Level Technology

    1. Front Matter
      Pages 549-549
    2. Balaram Ghosal, Richard Sigliano, Y. Kunimatsu
      Pages 551-576
    3. Mark J. Kuzawinski, Thomas R. Homa
      Pages 577-613
    4. Frank Andros
      Pages 614-655
    5. Marie S. Cole, Karl J. Puttlitz, Robert Lanzone
      Pages 656-701
    6. Puligandla Viswanadham, Tom Chung, Steven O. Dunford
      Pages 702-761
    7. Cynthia Milkovich
      Pages 762-803
    8. Phil Isaacs, Karl J. Puttlitz
      Pages 804-837
    9. Karl J. Puttlitz, Lewis S. Goldmann
      Pages 838-881
    10. Thomas H. Koschmieder, Andrew J. Mawer, Giülio Di Giacomo, Jasvir S. Jaspal
      Pages 882-945
    11. Reza Ghaffarian
      Pages 946-971
  5. Base Technology

    1. Front Matter
      Pages 973-973
    2. George Katopis, Dale Becker, Evan Davidson, Michael Nealon
      Pages 975-1010
    3. David L. Thomas, Daniel O’Connor, Jeffrey A. Zitz
      Pages 1011-1030
    4. Jeffrey A. Zitz, Randall G. Kemink, Bahgat Sammakia, Sanjeev Sathe, David J. Womac
      Pages 1049-1107
    5. D. R. Frear, K.-N. Tu
      Pages 1108-1144
  6. Back Matter
    Pages 1145-1188

About this book

Introduction

Microelectronic packaging has been recognized as an important "enabler" for the solid­ state revolution in electronics which we have witnessed in the last third of the twentieth century. Packaging has provided the necessary external wiring and interconnection capability for transistors and integrated circuits while they have gone through their own spectacular revolution from discrete device to gigascale integration. At IBM we are proud to have created the initial, simple concept of flip chip with solder bump connections at a time when a better way was needed to boost the reliability and improve the manufacturability of semiconductors. The basic design which was chosen for SLT (Solid Logic Technology) in the 1960s was easily extended to integrated circuits in the '70s and VLSI in the '80s and '90s. Three I/O bumps have grown to 3000 with even more anticipated for the future. The package families have evolved from thick-film (SLT) to thin-film (metallized ceramic) to co-fired multi-layer ceramic. A later family or ceramics with matching expansivity to sili­ con and copper internal wiring was developed as a predecessor of the chip interconnection revolution in copper, multilevel, submicron wiring. Powerful server packages have been de­ veloped in which the combined chip and package copper wiring exceeds a kilometer. All of this was achieved with the constant objective of minimizing circuit delays through short, efficient interconnects.

Keywords

Potential Scale Wafer development interconnect manufacturing material metal

Bibliographic information