Test Access Mechanism Optimization

Abstract

Test access is a major problem for core-based system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. An efficient test access architecture should also reduce test cost by minimizing test application time. In this chapter¹, we address several issues related to the design of optimal test access architectures that minimize testing time. These include the assignment of cores to test buses, the distribution of test data width between multiple test buses, and an analysis of test data width required to satisfy an upper bound on the testing time. Even though all these problems are shown to be NP-complete, they can be solved exactly for practical instances using integer linear programming (ILP). As a case study, the ILP models for two hypothetical but non-trivial systems are solved using a public-domain ILP software package.

This chapter is based in part on, K. Chakrabarty,“Optimal test access architectures for system-on-a-chip,” ACM Transactions on Design Automation of Electronic Systems, vol. 6, 26–49, January 2001. ©2001 ACM, Inc. Reprinted by permission.