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Test Resource Partitioning for System-on-a-Chip

  • Krishnendu Chakrabarty
  • Vikram Iyengar
  • Anshuman Chandra

Part of the Frontiers in Electronic Testing book series (FRET, volume 20)

Table of contents

  1. Front Matter
    Pages i-xii
  2. Introduction

    1. Front Matter
      Pages 1-1
    2. Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 3-15
  3. TRP For Test Hardware Optimization

    1. Front Matter
      Pages 17-17
    2. Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 19-43
    3. Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 45-64
    4. Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 65-93
  4. TRP For Testing Time Minimization

    1. Front Matter
      Pages 94-94
    2. Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 97-118
    3. Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 119-134
  5. TRP For Test Data Volume Reduction

    1. Front Matter
      Pages 135-135
    2. Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 137-178
    3. Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 179-201
    4. Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 203-216
    5. Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 217-221
  6. Back Matter
    Pages 223-232

About this book

Introduction

Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic.

SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols.

Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume.

Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.

Keywords

Hardware Standard automation circuit data compression development integrated circuit logic manufacturing mechanism optimization system on chip (SoC) testing

Authors and affiliations

  • Krishnendu Chakrabarty
    • 1
  • Vikram Iyengar
    • 1
  • Anshuman Chandra
    • 1
  1. 1.Department of Electrical and Computer EngineringDuke UniversityDurhamEngland

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-1113-7
  • Copyright Information Kluwer Academic Publishers 2002
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-5400-0
  • Online ISBN 978-1-4615-1113-7
  • Series Print ISSN 0929-1296
  • Buy this book on publisher's site