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Two-Level Logic Minimization

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Logic Synthesis and Verification

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 654))

Abstract

This chapter presents both exact and heuristic two-level logic minimization algorithms. For exact logic minimization, it shows various techniques to reduce the complexity of covering problems, discusses branching heuristics, and presents several methods to prune the recursions. For heuristic minimization, it presents the core procedures of the ESPRESSO minimizes Finally, the chapter surveys various works related to two-level logic minimization.

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Authors
  1. Olivier Coudert
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  2. Tsutomu Sasao
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Editor information

Editors and Affiliations

  1. Tufts University, USA

    Soha Hassoun

  2. Kyushu Institute of Technology, Japan

    Tsutomu Sasao

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Coudert, O., Sasao, T. (2002). Two-Level Logic Minimization. In: Hassoun, S., Sasao, T. (eds) Logic Synthesis and Verification. The Springer International Series in Engineering and Computer Science, vol 654. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0817-5_1

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  • DOI: https://doi.org/10.1007/978-1-4615-0817-5_1

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5253-2

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