Abstract
The basic ideas for the optimization of a signal net are briefly reviewed in this chapter. To begin with, there is the delay optimization of a simple point-to-point wire driven by a single logic stage, considering the effects of wire capacitance and wire resistance (Fig. 5.1a). Next, the extended problem of optimizing a multistage logic path (which includes several point-to-point wires) is examined (Fig. 5.1b). Finally, the more general problem where the point-to-point wire segments are replaced by multisink interconnect trees is presented (Fig. 5.1c).
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Moiseev, K., Kolodny, A., Wimer, S. (2015). Net-by-Net Wire Optimization. In: Multi-Net Optimization of VLSI Interconnect. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0821-5_5
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