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Multi-Net Optimization of VLSI Interconnect

  • Konstantin Moiseev
  • Avinoam Kolodny
  • Shmuel Wimer

Table of contents

  1. Front Matter
    Pages i-xvi
  2. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
    Pages 1-9
  3. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
    Pages 11-16
  4. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
    Pages 17-34
  5. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
    Pages 35-42
  6. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
    Pages 43-61
  7. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
    Pages 63-106
  8. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
    Pages 107-165
  9. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
    Pages 167-194
  10. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
    Pages 195-219
  11. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
    Pages 221-222
  12. Back Matter
    Pages 223-233

About this book

Introduction

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.
 • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization;
• Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools;
• Includes mathematical properties and conditions for optimality of layout, describes and analyses algorithmic solutions, and supplements analysis with examples taken from state-of-the-art chips.

This book addresses an intriguing engineering challenge, namely the design of an enormous maze of wires, which run in about a dozen metal layers above billions of transistors in a modern processor. The physical insight, mathematical rigor and methodological approach described in the book, are essential for engineers and computer architects, as they develop new systems of ever-increasing complexity and migrate them to new generations of device technologies.  The Authors of this book didn’t only develop the academic methodologies, but actually developed CAD tools, and implemented their tools and methodologies to design VLSI chips. I had the privilege to work with them.

--Mooly Eden, Senior Vice President, Intel Corporation; President, Intel Israel

The speed, power, area, and reliability of high performance integrated circuits are determined by the on-chip interconnect. With the publication of this book, an important niche has been filled; that is local and global on-chip interconnect optimization. This book provides a theoretical basis for the practical design of the key issue in modern integrated circuits, the on-chip interconnect.

--Eby G. Friedman, Distinguished Professor, University of Rochester

Keywords

Embedded Systems Interconnect optimization Interconnect scalability Interconnection networks Multi-Net Optimization of VLSI Interconnect Networks on Chip On-chip interconnect VLSI Interconnect

Authors and affiliations

  • Konstantin Moiseev
    • 1
  • Avinoam Kolodny
    • 2
  • Shmuel Wimer
    • 3
  1. 1.IntelHaifaIsrael
  2. 2.TechnionHaifaIsrael
  3. 3.Bar-Ilan UniversityRamat-GanIsrael

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4614-0821-5
  • Copyright Information Springer Science+Business Media New York 2015
  • Publisher Name Springer, New York, NY
  • eBook Packages Engineering
  • Print ISBN 978-1-4614-0820-8
  • Online ISBN 978-1-4614-0821-5
  • Buy this book on publisher's site