Abstract
Analog and mixed-signal circuits are very sensitive to the process variations as many matchings are required. This situation becomes worse as technology continues to scale to 90nm and below owing to the increasing process-induced variability[122, 148]. Transistor-level mismatch is the primary obstacle to reach a high yield rate for analog designs in sub-90nm technologies. For example, due to an inverse-square-root-law dependence with the transistor area, the mismatch of CMOS devices nearly doubles for each process generation less than 90nm [80, 104]. Since the traditional worst-case- or corner-case-based analysis is too pessimistic to sacrifice the speed, power, and area, the statistical approach [133] thereby becomes a trend to estimate the analog mismatch and performance variations. The variations in the analog components can come from systematic (or global spatial variation) ones and stochastic (or local random variation) ones. In this chapter, we model both variations as the parameter intervals on the components of analog circuits.
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Shen, R., Tan, S.XD., Yu, H. (2012). Performance Bound Analysis of Variational Linearized Analog Circuits. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_14
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