Abstract
Sun Microsystems® has designed a RISC architecture, called Scalable Processor ARChitecture (SPARC™), and has implemented that architecture with the Sun-4™ family of supercomputing workstations and servers. SPARC stands for, emphasizing its applicability to large as well as small machines. SPARC systems have an open computer architecture—the design specification is published, and other vendors are producing microprocessors implementing the design. As with the Network File System (NFS™), we hope that the intelligent and aggressive nature of the SPARC design will become an industry standard.
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Notes
By comparable we mean architectures that cost about the same to implement. A Cray-2 supercomputer is not comparable to an IBM® PC in this sense.
The first implementation has 7 register windows with 24 registers each (but count only 16 since 8 overlap), plus 8 global registers, for a total of 120 registers.
D. Ungar, R. Blau, P. Foley, A.D. Samples, D. Patterson, “Architecture of SOAR: Smalltalk on a RISC,” in Proceedings of the 11th Annual International Symposium on Computer Architecture, Ann Arbor, 1984.
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© 1991 Sun Microsystems, Inc.
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Tuthill, B., Tuck, R. (1991). A RISC Tutorial. In: Catanzaro, B.J. (eds) The SPARC Technical Papers. Sun Technical Reference Library. Springer, New York, NY. https://doi.org/10.1007/978-1-4612-3192-9_3
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DOI: https://doi.org/10.1007/978-1-4612-3192-9_3
Publisher Name: Springer, New York, NY
Print ISBN: 978-0-387-97634-1
Online ISBN: 978-1-4612-3192-9
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