The SPARC Technical Papers

1. Front Matter

   Pages i-xvi

   PDF

2. The SPARC Architecture

   1. Front Matter

      Pages 1-1

      PDF

   2. The Scalable Processor Architecture (SPARC)

      • Robert B. Garner

      Pages 3-31

   3. The Scalable Processor Architecture (SPARC)

      • Robert B. Garner, Anant Agrawal, Fayé Briggs, Emil W. Brown, David Hough, Bill Joy et al.

      Pages 33-47

   4. A RISC Tutorial

      • Bill Tuthill, Richard Tuck

      Pages 49-66

   5. Why RISC Has Won

      • David R. Ditzel

      Pages 67-70

   6. SPARC: A Total Solution for RISC

      • Brian Case

      Pages 71-80

   7. The Role of RISC in Advanced Computer Design

      • David R. Ditzel

      Pages 81-88

3. SPARC Implementations

   1. Front Matter

      Pages 89-89

      PDF

   2. First 32-Bit SPARC-Based Processors Implemented in High-Speed CMOS

      • Masood Namjoo

      Pages 91-99

   3. SPARC: An ASIC Solution for High-Performance Microprocessors

      • Anant Agrawal, Robert B. Garner, Donald C. Jackson

      Pages 101-119

   4. SPARC Implementations: ASIC vs. Custom Design

      • Masood Namjoo

      Pages 121-129

   5. Sunrise: A High-Performance 32-Bit Microprocessor

      • Masood Namjoo, Anant Agrawal

      Pages 131-149

   6. CMOS Custom Implementation of the SPARC Architecture

      • M. Namjoo, F. Abu-Nofal, D. Carmean, R. Chandramouli, Y. Chang, J. Goforth et al.

      Pages 151-157

   7. CMOS Gate-Array Implementation of the SPARC Architecture

      • Masood Namjoo, Anant Agrawal, Donald C. Jackson, L. Quach

      Pages 159-171

   8. Implementing SPARC: A High-Performance 32-Bit RISC Microprocessor

      • Masood Namjoo, Anant Agrawal

      Pages 173-189

   9. Design Considerations for a Bipolar Implementation of SPARC

      • Anant Agrawal, Emil W. Brown, Joseph Petolino, James R. Peterson

      Pages 191-200

   10. Bipolar ECL Implementation of SPARC

       • Anant Agrawal, Emil W. Brown, Dave Murata, Joseph Petolino

       Pages 201-211

   11. Implementing SPARC in ECL

       • Emil W. Brown, Anant Agrawal, Trevor Creary, Michael F. Klein, Dave Murata, Joseph Petolino

       Pages 213-232

   12. SPARC: An Open RISC Architecture

       • Kevin M. Kitagawa, Raymond M. Leong

       Pages 233-245

With the SPARC (Scalable Processor ARChitecture) architecture and system software as the underlying foundation, Sun Microsys­ terns is delivering a new model of computing-easy workgroup computing-to enhance the way people work, automating processes across groups, departments, and teams locally and globally. Sun and a large and growing number of companies in the computer industry have embarked on a new approach to meet the needs of computer users and system developers in the 1990s. Originated by Sun, the approach targets users who need a range of compatible computer systems with a variety of application soft­ ware and want the option to buy those systems from a choice of vendors. The approach also meets the needs of system developers to be part of a broad, growing market of compatible systems and software-developers who need to design products quickly and cost-effecti vel y. The SPARe approach ensures that computer systems can be easy to use for all classes of users and members of the workgroup, end users, system administrators, and software developers. For the end user, the SPARC technologies facilitate system set-up and the daily use of various applications. For the system administrator supporting the computer installation, setting up and monitoring the network are easier. For the software developer, there are ad­ vanced development tools and support. Furthermore, the features of the SPARC hardware and software technologies ensure that SPARC systems and applications play an important role in the years to come.

• ASIC
• CMOS
• Interface
• architecture
• compiler
• computer
• microprocessor

• Sun Microsystems, Inc., Mountain View, USA

  Ben J. Catanzaro

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