Abstract
Sun Microsystems’ SPARC architecture, based on the RISCs and SOAR architectures developed at UC Berkeley, was designed for easily pipelined, cost-effective, high-performance, multi-technology implementations. The goal is that the cost/performance ratio of successive implementations should scale with, or track, improvements in circuit technology while remaining ahead of CISC-based systems. The simple instruction set, well-matched to compiler technology, allows for implementations with very high MIPS rates and short development cycles.
The combined integer and floating-point architecture includes multiprocessor, coprocessor, and tagged arithmetic support. System functions, such as an MMU, are not integrated into the architecture.
Sun Microsystems is encouraging other companies to implement SPARC. Its first implementation is a pair of 20K-gate CMOS gate arrays plus two float chips; higher-performance custom CMOS and ECL are under development.
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© 1991 Sun Microsystems, Inc.
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Garner, R.B. et al. (1991). The Scalable Processor Architecture (SPARC). In: Catanzaro, B.J. (eds) The SPARC Technical Papers. Sun Technical Reference Library. Springer, New York, NY. https://doi.org/10.1007/978-1-4612-3192-9_2
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DOI: https://doi.org/10.1007/978-1-4612-3192-9_2
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