Abstract
DC resistance measurements of precision and parasitic resistors form an important part of CMOS technology characterization. Sheet resistances are measured to monitor and control material properties such as film thickness and doping levels in silicon layers. Resistance measurements are utilized in monitoring product yield loss caused by electrical opens in metal wires and inter-level vias, or shorts between neighboring wires. In metrology and for process tuning applications, linewidths are extracted from resistance measurements. For CMOS circuit simulations, electrical models of resistors are constructed based on data collected from test structures.
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References
Schroder DK (2006) Semiconductor material and device characterization, 3rd edn. Wiley, Hoboken, NJ
Lindley D (2004) Degrees Kelvin. Joseph Henry, Washington, DC
Pauw van der LJ (1958) A method of measuring specific resistivity and hall effect of discs of arbitrary shape. Philips Res Rep 13:1–9
Versnel W (1979) Analysis of the Greek cross, a Van der Pauw structure with finite contacts. Solid State Electron 22:911–914
Application Note 4156-11 Precision measurement of metal line width in sub-quarter micron interconnect systems. Agilent Technologies. Available via http://www.home.agilent.com/agilent/facet.jspx?t=80030.k.1&cc=US&lc=eng&sm=g&pageMode=TM. Accessed 3 Feb 2011
Stapper CH, Rosner RJ (1995) Integrated circuit yield management and yield analysis: development and implementation. IEEE Trans Semicond Manuf 8:95–102
Kuo W, Kim T (1999) An overview of manufacturing yield and reliability modeling for semiconductor products. Proc IEEE 87:1329–1344
Verzi B (2009) Considerations for parallel and array test patterns. In: International conference on microelectronic test structures, Oxnard, 30 Mar 2009
Walton AJ, Gammie W, Fallon M, Stevenson JTM, Holwill RJ (1991) An interconnect scheme for reducing the number of contact pads on process control chips. IEEE Trans Semiconduct Manuf 4:233–240
Ward D, Walton AJ, Gammie WG, Holwill RJ (1992) The use of a digital multiplexer to reduce process control chip pad count. Proceedings of the 1992 IEEE International conference on microelectronic test structures, 1992, pp. 129–133
Ketchen MB, Bhushan M, Costrini G (2009) Addressable arrays implemented with one metal level for MOSFET and resistor variability characterization. Proceedings of the 2009 IEEE International conference on microelectronic test structures, 2009, pp. 13–18
Hess C, Inani A, Lin Y, Squicciarini M, Lindley R, Akiya N (2006) Scribe characterization vehicle test chip for ultra fast product wafer yield monitoring. Proceedings of the 2006 IEEE international conference on microelectronic test structures, 2006, pp. 110–115
Hess C, Squicciarini M, Yu S, Burrows J, Cheng J, Lindley R et al (2008) High density test structure array for accurate detection and localization of soft fails. Proceedings of the 2008 IEEE International conference on microelectronic test structures, 2008, pp. 131–136
Karthikeyan M, Fox S, Cote W, Yeric G, Hall M, Garcia J et al (2006) A 65 nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software. Proceedings of the 2006 IEEE international conference on microelectronic test structures, 2006, pp. 104–109
Cabrini A, Cantarelli D, Cappelletti P, Casiraghi R, Maurelli A, Pasotti M et al (2006) A test structure for contact and via failure analysis in deep-submicrometer CMOS technologies. IEEE Trans Semicond Manuf 19:57–66
Tian W, Steinmann P, Beach E, Khan I, Madhani P (2008) Mismatch characterization of a high precision resistor array test structure. Proceedings of the 2008 IEEE international conference on microelectronic test structures, 2008, pp. 11–16
Doong KY-Y, Hsieh S, Lin S-C, Shen B, Cheng J-Y, Kwai D-M et al (2001) Addressable failure site test structures (AFS-TS) for CMOS processes: design guidelines, fault simulation, and implementation. IEEE Trans Semicond Manuf 14:338–355
Doong KYY, Bordelon J, Chang K-J, Hung LJ, Liao CC, Lin SC et al (2006) Field-configurable test structure array (FC-TSA): enabling design for monitor, model and manufacturability. Proceedings of the 2006 IEEE international conference on microelectronic test structures, 2006, pp. 98–103
Enderling S, Brown CLIII, Smith S, Dicks MH, Stevenson JTM, Mitkova M et al (2006) Sheet resistance measurement of non-standard cleanroom materials using suspended Greek cross test structures. IEEE Trans Semicond Manuf 19:2–9
Shulver BJR, Bunting AS, Gundlach AM, Haworth LI, Ross AWS, Smith S et al (2008) Extraction of sheet resistance and line width from all-copper ECD test structures fabricated from silicon preforms. IEEE Trans Semicond Manuf 21:495–503
Smith S, Tsiamis A, McCallum M, Hourd AC, Stevenson JTM, Walton AJ et al (2009) Comparison of measurement techniques for linewidth metrology on advanced photomasks. IEEE Trans Semicond Manuf 22:72–79
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Bhushan, M., Ketchen, M.B. (2011). Resistors. In: Microelectronic Test Structures for CMOS Technology. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9377-9_3
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DOI: https://doi.org/10.1007/978-1-4419-9377-9_3
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