Abstract
In this chapter a wafer-level thinning technique is presented, where, similar to what is discussed in Chapter 8, epitaxial growth of silicon (Si) determines the final chip thickness. A combination of backside grinding and selective wet chemical etching is used for thinning down the initial substrate. Since wafer bonding and grinding were thoroughly addressed in Chapters 4 and 5, this subsection deals only with the other key processing steps, namely the wet chemical etching of Si and the epitaxial growth of highly boron-doped Si required to trigger the etch selectivity. Finally, process parameters and significant results based on this technique are summarised.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Alexander Kaiser (2007) Dreidimensionale Systemintegration: technologische Entwicklung und Anwendung. Ph.D. dissertation, Cuvillier Verlag, Göttingen, Germany
Ninković J, Eckhart R, Hartmann R, Holl P, Koitsch C, Lutz G, Merck C, Mirzoyan R, Moser H-G, Otte A-N, Richter R, Schaller G, Schopper F, Soltau H, Teshima M, Vâlceanu G (2007) The avalanche drift diode a back illumination drift silicon photomultiplier. Nucl Instrum Methods Phys A 580:1013–1015
Campbell SA, Lewerenz HJ (1998) Semiconductor micromachining: techniques and industrial applications, vol 2. Wiley, West Sussex
Seidel H, Csepregi L, Heuberger A, Baumgärtel H (1990) Anisotropic etching of crystalline silicon in alkaline solutions. J Electrochem Soc 137:3626–3632
Cho D (Fall 2002) Bulk micromachining. Class presentation notes, for course Introduction to MEMS
Finne RM, Klein DL (1967) A water-amine-complexing agent system for etching silicon. J Electrochem Soc 114:965–968
Steckl AJ, Mogul HC, Mogren S (1992) Localized fabrication of Si nanostructures by focused ion beam implantation. Appl Phys Lett 60:1833–1835
Wallman L, Bengtsson J, Danielsen N, Laurell T (2002) Electrochemical etch-stop technique for silicon membranes with p- and n-type regions and its application to neural sieve electrodes. J Micromech Microeng 12:265–270
Kucytowski J, Wokulska K (2005) Lattice parameter measurements of boron doped Si single crystals. Cryst Res Technol 40:424–428
Lin W, Hill DW, Paulnack CL, Kelly MJ (1991) Misfit stress in p/p + epitaxial silicon wafers: effect and elimination. In: Defects in silicon II. The Electrochemical Society, Pennington, pp 163–171
Föll H. Defects in crystals, Hyperscript, Faculty of Engineering, University of Kiel, http://www.tf.unikiel.de/matwis/amat/def_en/index.html
Desmond C (1993) Thin-film silicon-on-insulator by bond and etch back (BESOI). Ph.D. dissertation, Department of Electrical and Computer Engineering, University of California, Davis
Maszara WP, Thompson T (1992) Strain compensation by Ge in B-doped silicon epitaxial films. J Appl Phys 9:4477–4479
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Angelopoulos, E.A., Kaiser, A. (2011). Epitaxial Growth and Selective Etching Techniques. In: Burghartz, J. (eds) Ultra-thin Chip Technology and Applications. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7276-7_6
Download citation
DOI: https://doi.org/10.1007/978-1-4419-7276-7_6
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4419-7275-0
Online ISBN: 978-1-4419-7276-7
eBook Packages: EngineeringEngineering (R0)