Power Management Architecture in McNoC

  • Jean-Michel Chabloz
  • Ahmed Hemani


In this chapter we present the power management architecture of the McNoC platform. The power management architecture of McNoC offers distributed Dynamic Voltage Frequency Scaling (DVFS) and power down services to the platform at a fine level of granularity, allowing independent setting of frequency and supply voltage to all switch and resource nodes in the platform. The design style enables hierarchical physical design and solves the clock-domain-crossing problem with a solution based on rationally-related frequencies, which avoids the overhead associated with handshake. The architecture allows arbitrary power management regions to be defined and region-wide power management commands affecting all nodes in a region can be issued by the software layer that we call as Power Management Intelligence (PMINT).


Supply Voltage Clock Cycle Power Management Receiver Clock Configuration Option 
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  1. 1.
    International Technology Roadmap for Semiconductors Report, 2009Google Scholar
  2. 2.
    J. M. Rabaey, “Digital Integrated Circuits: A Design Perspective,” Prentice Hall, 1995Google Scholar
  3. 3.
    A. P. Niranjan and P. Wiscombe, “Islands of synchronicity, a design methodology for SoC design,” Design, Automation and Test in Europe Conference and Exhibition, 2004Google Scholar
  4. 4.
    S. Herbert and D. Marculescu, “Analysis of Dynamic Voltage/Frequency Scaling in Chip-Multiprocessors,” ISLPED 2007Google Scholar
  5. 5.
    P. Teehan et al., “A Survey and Taxonomy of GALS Design Styles,” Design & Test of Computers, IEEE, vol.24, no.5, pp.418-428, Sept.-Oct. 2007Google Scholar
  6. 6.
    Nostrum home page -
  7. 7.
    E. Nilsson, “Design and implementation of a hot-potato switch in a network on chip,” Master’s thesis, Department of Microelectronics and Information Technology, KTH, 2002Google Scholar
  8. 8.
    A. Hemani et al., “Lowering power consumption in clock by using globally asynchronous locally synchronous design style,” Design Automation Conference, 1999Google Scholar
  9. 9.
    I. E. Sutherland and J. Ebergen, “Computers Without Clocks,” Scientific American, Aug. 2002Google Scholar
  10. 10.
    S. Borkar, “Does asynchronous logic design really have a future?,” EE Times, 2003Google Scholar
  11. 11.
    D. M. Chapiro, “Globally Asynchronous Locally-Synchronous Systems,” PhD thesis, Stanford University, Oct. 1984Google Scholar
  12. 12.
    K. Y. Yun and R. P. Donohue, “Pausible clocking: a first step toward heterogeneous systems,” IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1996Google Scholar
  13. 13.
    J. Muttersbach et al., “Practical design of globally-asynchronous locally-synchronous systems,” International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2000Google Scholar
  14. 14.
    J. M. Chabloz and A. Hemani, “A Flexible Interface for Rationally-Related Frequencies,” ICCD 2009Google Scholar
  15. 15.
    J. M. Chabloz and A. Hemani, “Distributed DVFS with Rationally-Related Frequencies and Quantized Voltage Levels,” ISLPED 2010Google Scholar
  16. 16.
    L. H. Chandrasena et al., “An Energy Efficient Rate Selection Algorithm for Voltage Quantized Dynamic Voltage Scaling,” ISSS 2001Google Scholar
  17. 17.
    M. Putic et al., “Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design,” ICCD 2009Google Scholar
  18. 18.
    E. Beigne et al. “Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC,” NOCS 2008Google Scholar
  19. 19.
    Cadence SoC Encounter User GuideGoogle Scholar
  20. 20.
    V. Gutnik and A. Chandrakasan, “Embedded power supply for low-power DSP,” in IEEE Transactions on VLSI Systems, 1997Google Scholar
  21. 21.
    J. M. Chabloz and A. Hemani, “Lowering the Latency of Interfaces for Rationally-Related Frequencies,” ICCD 2010Google Scholar
  22. 22.
    I. Miro Panades et al., “Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture,” NoCS 2008Google Scholar
  23. 23.
    D. Kim et al., “Asynchronous FIFO Interfaces for GALS On-Chip Switched Networks,” International SoC Design Conference, 2005Google Scholar
  24. 24.
    G. Liang and A. Jantsch, “Adaptive Power Management for the On-Chip Communication Network,” Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference onGoogle Scholar
  25. 25.
    S. R. Vangal et al., “An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol.43, no.1, Jan. 2008Google Scholar
  26. 26.
    T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas,” IEEE J. of solid-state circuits, 1990Google Scholar
  27. 27.
    A. Chakraborty and M. R. Greenstreet, “Efficient self-timed interfaces for crossing clock domains,” International Symposium on Asynchronous Systems and Circuits, 2003Google Scholar
  28. 28.
    J. Mekie et al., “Interface Design for Rationally Clocked GALS Systems,” International Symposium on Asynchronous Systems and Circuits, 2006Google Scholar
  29. 29.
    L. F. G. Sarmenta, “Synchronous Communication Techniques for Rationally Clocked Systems,” Master’s thesis, MIT, 1995Google Scholar
  30. 30.
    J. Carlsson et al., “A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems,” Norchip Conference, 2006Google Scholar
  31. 31.
    E. Amini et al., “Globally asynchronous locally synchronous wrapper circuit based on clock gating,” Symposium on Emerging VLSI Technologies and Architectures, 2006Google Scholar
  32. 32.
    M. R. Greenstreet, “Implementing a STARI chip,” International Conference on Computer Design, 1995Google Scholar
  33. 33.
    F. Mu and C. Svensson, “Self-tested self-synchronization circuit for mesochronous clocking,” IEEE Transactions on Analog and Digital Signal Processing, vol.48, no.2, pp.129-140, Feb. 2001CrossRefGoogle Scholar
  34. 34.
    D. Mangano et al., “Skew Insensitive Physical Links for Network on Chip,” 1st International Conference on Nano-Networks and Workshops, Sep. 2006Google Scholar
  35. 35.
    I. Loi et al., “Developing Mesochronous Synchronizers to Enable 3D NoCs,” DATE, 2008Google Scholar
  36. 36.
    C. E. Cummings and P. Alfke, “Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons,” Synopsys Users Group Conference, 2002Google Scholar
  37. 37.
    N. Wingen, “What If You Could Design Tomorrow’s System Today?,” Design, Automation & Test in Europe Conference & Exhibition, 2007Google Scholar
  38. 38.
    R. Ginosar, “Fourteen ways to fool your synchronizer,” International Symposium on Asynchronous Systems and Circuits, 2003Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.ES DepartmentSchool of ICT, KTHKistaSweden

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