Abstract
Many applications require wide tuning range phase-locked loops (PLLs) to generate pure and well controlled periodic signals [1]-[3]. PLLs might be used for controlling the operation condition of specific parts of a system such as continuous-time filters, as well [4].
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
F. Gardner, “Charge-pump phase-locked loops,” in IEEE Transactions on Communication, vol. 28, pp. 1849–1858, Nov. 1980
T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, Second Ed., 2004
J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 11, pp. 1723–1732, Nov. 1996
A. Tajalli, P. Muller, and Y. Leblebici, “A power-efficient clock and data recovery circuit in 0.18μm CMOS technology for multi-channel short-haul optical data communication,” IEEE J. Solid-State Circuits, vol. 42, pp. 2235–2244, Oct. 2007
T. Ebuchi, Y. Komatsu, T. Okamoto, Y. Arima, Y. Yamada, K. Sogawa, K. Okamoto, T.Morie, T. Hirata, S. Dosho, and T. Yoshikawa, “A 125-1250 MHz process-independent adaptive bandwidth spread spectrum clock generator with digital controlled self-callibration,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 763–772, Mar. 2009
A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Kluwer, 1995
M. Mansuri and C. -K. K. Yang, “A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1804–1812, Nov. 2003
J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas, “Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795–1803, Nov. 2003
H. Rategh and T. H. Lee, Multi-GHz Frequency Synthesis & Division, Kluwer, 2001
T. Wu, P. K. Hanumolu, K. Mayaram, U.-K. Moon, “Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp.427–435, Feb. 2009
A. Tajalli, P. Torkzadeh, and M. Atarodi, “A wide tuning range, fractional multiplying delay-locked loop topology for frequency hopping applications,” in Analog Integrated Circuits and Signal Processings, vol. 46, no. 3, pp. 203–214, Mar. 2006
M. Brownlee, P. K. Hanumolu, K. Mayaram, U. -K. Moon, “A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp.2720–2728, Dec. 2006
G. Yan, C. Ren, Z. Gzo, Q. Ouyang, and Z. Chang, “A self-biased PLL with current-mode filter for clock generation,” in IEEE International Solid-State Circuits Conference (ISSCC), pp. 420–421, Feb. 2005
P. K. Hanumolu, M. Brownlee, K. Mayaram, and U. -K. Moon, “Analysis of charge-pump phase-locked loops,” in IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 51, no. 9, pp. 1665–1674, Sep. 2004
S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, “Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers,” in Symposium on VLSI Circuits Digest of Technical Papers, pp. 124–127, Jun. 2000
B. Razavi, “Monolithic phase-locked loops and clock recovery circuits: theory and design,” Wiley, 1996
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Tajalli, A., Leblebici, Y. (2010). Wide Tuning Range PLL. In: Extreme Low-Power Mixed Signal IC Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6478-6_10
Download citation
DOI: https://doi.org/10.1007/978-1-4419-6478-6_10
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4419-6477-9
Online ISBN: 978-1-4419-6478-6
eBook Packages: EngineeringEngineering (R0)