Abstract
This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1–2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2N C ) in which M, k, and N C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between two consecutive integer numbers. Operating in 2.5 GHz, total circuit including digital part consumes 15.5 mW from 1.8 V supply voltage. At the proposed architecture, reference clock is injected into a ring oscillator in specified times and to the specified delay-stages to synthesize the fractional frequency multiplication as well as resetting the accumulated jitter during previous cycles. Operating in maximum speed, simulated RMS (root-mean-square) and PTP (peak-to-peak) jitter values are 1.8 and 14.5 ps, respectively, while the settling time is 5 us.
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Armin Tajalli received the B.Sc. from Sharif University of Technology (SUT), Tehran, Iran, in 1997, and M.Sc. from Tehran Polytechnic University, Tehran, Iran, in 1999.
From 1998 he has joint Emad Co. as a senior design engineer where he has worked on several industrial and R&D projects on analog and mixed-mode ICs. He received the award of the Best Design Engineer from Emad Co., 2001, the Kharazmi Award of Industrial Research and Development, Iran, 2002, and Presidential Award of the Best Iranian Researchers, in 2003. He is now working toward his Ph.D. degree at SUT. His current interests are design of high speed circuits for telecommunication systems.
Pooya Torkzadeh was born in Isfahan, on April 21, 1980. He received the B.Sc. degree from Isfahan University of Technology (IUT), Isfahan, in 2002 and the M.Sc. degree from Sharif University of Technology (SUT), Tehran, in 2004, both in electrical engineering. From 2002 to 2004, he was an Assistant with SUT and the member of Sharif Integrated Circuit And System Group (SICAS). His major activities are in Electronics Integrated Circuit Designing and Digital Signal Processing (DSP). He specializes in CMOS Integrated Circuits particularly for Clock Generation, Clock-Data Recovery Systems, and Sigma-Delta Analogue to Digital Converter Applications.
Mojtaba Atarodi received the B.S.E.E. from Amir Kabir University of Technology (Tehran Polytechnic) in 1985, and M.Sc. degree in electrical engineering from the University of California, Irvine, in 1987. He received the Ph.D. degree from the University of Southern California (USC) on the subject of analog IC design in 1993.
From 1993 to 1996 he worked with Linear Technology Corporation as a senior analog design engineer. Since then, he has been consulting with different IC companies. He is currently a visiting professor at Sharif University of Technology. He has published more than 30 technical papers in the area of analog and mixed-signal integrated circuit design as well as analog CAD tools.
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Tajalli, A., Torkzadeh, P. & Atarodi, M. A Wide Tuning Range, Fractional Multiplying Delay-Locked Loop Topology for Frequency Hopping Applications. Analog Integr Circ Sig Process 46, 203–214 (2006). https://doi.org/10.1007/s10470-006-1276-7
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DOI: https://doi.org/10.1007/s10470-006-1276-7