FPGA Design pp 29-40 | Cite as

Board Design



In order to meet the fast performance and high bandwidth of today’s system designs, FPGA devices are providing a large number of pins with increasingly faster switching speeds. These higher package pin counts, together with the fact that the devices support many different I/O standards and support different package types, creates a challenge in successfully creating the FPGA pin-out efficiently and correctly. The cost of a board re-spin, due to a problem with the pin-out, is expensive in terms of both the cost of the board re-spin and the impact on the project schedule.


Migration Expense PCBs 

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Altera CorporationSan JoseUSA

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