FPGA Design

1. Front Matter

   Pages i-xv

   PDF

2. Best Practices for Successful FPGA Design

   • Philip Simpson

   Pages 1-3

3. Project Management

   • Philip Simpson

   Pages 5-7

4. Design Specification

   • Philip Simpson

   Pages 9-13

5. Resource Scoping

   • Philip Simpson

   Pages 15-21

6. Design Environment

   • Philip Simpson

   Pages 23-28

7. Board Design

   • Philip Simpson

   Pages 29-40

8. Power and Thermal Analysis

   • Philip Simpson

   Pages 41-50

9. RTL Design

   • Philip Simpson

   Pages 51-78

10. IP and Design Reuse

    • Philip Simpson

    Pages 79-90

11. The Hardware to Software Interface

    • Philip Simpson

    Pages 91-94

12. Functional Verification

    • Philip Simpson

    Pages 95-106

13. Timing Closure

    • Philip Simpson

    Pages 107-132

14. In-System Debug

    • Philip Simpson

    Pages 133-144

15. Design Sign-Off

    • Philip Simpson

    Pages 145-146

16. Back Matter

    Pages 147-151

    PDF

In August of 2006, an engineering VP from one of Altera’s customers approached Misha Burich, VP of Engineering at Altera, asking for help in reliably being able to predict the cost, schedule and quality of system designs reliant on FPGA designs. At this time, I was responsible for defining the design flow requirements for the Altera design software and was tasked with investigating this further. As I worked with the customer to understand what worked and what did not work reliably in their FPGA design process, I noted that this problem was not unique to this one customer. The characteristics of the problem are shared by many Corporations that implement designs in FPGAs. The Corporation has many design teams at different locations and the success of the FPGA projects vary between the teams. There is a wide range of design experience across the teams. There is no working process for sharing design blocks between engineering teams. As I analyzed the data that I had received from hundreds of customer visits in the past, I noticed that design reuse among engineering teams was a challenge. I also noticed that many of the design teams at the same Companies and even within the same design team used different design methodologies. Altera had recently solved this problem as part of its own FPGA design software and IP development process.

• Embedded Systems
• FPGA Debugging
• FPGA design
• FPGA design flow
• Reuse
• System-level design
• Team-based design
• design automation
• electronic design automation

• Altera Corporation, San Jose, USA

  Philip Simpson

Phil Simpson is Altera’s senior manager for software technical marketing and product planning. In this role, Simpson is responsible for Altera’s Quartus II software and third-party EDA interfaces product planning and the creation of the Altera design flow software roadmap. Prior to joining Altera in 1996, Simpson held several engineering roles at various EDA and semiconductor companies, including EDA Solutions, Data I/O and Lucas Aerospace. Simpson holds a BS (with honors) in Electrical & Electronic Engineering from City University, London and an MSC (with distinction) in system design from the University of Central England, Birmingham, England.

Policies and ethics