Floorplanning: VLSI and other Applications

Abstract

Once the circuit is available in the form of gate-level netlist, or even before at RTL if the area occupied by each block can be estimated or measured with some certainty alongwith the number of terminals required by each block, then the next step in completing the layout is to assign a specific shape to each block and arrange the blocks minimizing the total area of the chip. This problem of block level arrangement to minimize total chip area under the constraints of chip aspect ratio and block areas is called the VLSI Floorplanning problem. For further details please refer to [109, 115].

The input to the floorplanner is a set of blocks, the area and aspect ratio of each block, possible shapes of each block, and the number of terminals for each block. In this chapter we develop a floorplanner based on the sequence-pair method [91].