Optimization based sizing methods allow automating the synthesis of analog circuits. Automated analog circuit synthesis techniques depend on fast and reliable estimation of circuit performance. This paper presents a highly accurate method of estimating performances by constructing models of the circuit matrix instead of the traditionally used performance models. Device matching in analog circuits is utilized to identify identical elements in the circuit matrix and reduce the number of elements to be modeled. Experiments conducted on benchmark circuits demonstrate the effectiveness of the method in achieving correct performance prediction. Results show that the performances can be predicted within a mean error of 0.1% compared to a SPICE simulation. Techniques such as hashing and near neighbor searches are proposed to expedite the matrix model evaluation procedure. These techniques avoid recomputations by saving previously visited solutions. The procedure is used for synthesizing analog circuits from various specifications such as performance parameters, frequency response. The proposed method gives accurate results for synthesis for various types of circuit specifications.
Chapter PDF
Similar content being viewed by others
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
M. Krasnicki, R. Phelps, R. A. Rutenbar, and L. R. Cariey, “MAELSTROM: Efficient simulation-based synthesis for custom analog cells,” in Proc. - 36th Design Automation Conference, pp. 945–950, 1999.
M. J. Krasnicki, R. Phelps, J. R. Hellums, M. McClung, R. A. Rutenbar, and L. R. Carley, “ASF: a practical simulation-based methodology for the synthesis of custom analog circuits,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 350–357, 2001.
M. Ranjan, W. Verhaegen, A.Agarwal, H.Sampath, R.Vemuri, and G. Gielen, “Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models,” in Proc. DATE, p. 10604, 2004.
T. McConaghy and G. Gielen, “Double-strength CAFFEINE: Fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns,” in Proceedings of the conference on Design, Automation and Test in Europe, pp. 269–274, 2006.
G. Wolfe and R. Vemuri, “Extraction and use of neural network models in automated synthesis of operational amplifiers,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 22, pp. 198–212, Feb. 2003.
S. Doboli, G. Gothoskar, and A. Doboli, “Extraction of piecewise-linear analog circuit models from trained neural networks using hidden neuron clustering,” in Proceedings of the conference on Design, Automation and Test in Europe, p. 11098, 2003.
T. Kiely and G. Gielen, “Performance modeling of analog integrated circuits using least-squares support vector machines,” in Proceedings of the conf. on Design, Automation and Test in Europe, p. 10448, 2004.
F. D. Bernardinis, M. I. Jordan, and A. S. Vincentelli, “Support vector machines for analog circuit performance representation,” in Proc. DAC ’03, pp. 964–969, 2003.
M. Ding and R. Vemuri, “A combined feasibility and performance macromodel for analog circuits,” in Proc. 42nd Design Automation Conference, pp. 63–68, 2005.
D. Han and A. Chatterjee, “Adaptive response surface modeling-based method for analog circuit sizing,” in Proceedings. IEEE International SOC Conference, pp. 109–112, 2004.
G. Wolfe and R. Vemuri, “Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 931–938, 2004.
H. Liu, A. Singhee, R. A. Rutenbar, and L. R. Carley, “Remembrance of circuits past: macromodeling by data mining in large analog design spaces,” in Proc. DAC ’02, pp. 437–442, 2002.
T. McConaghy and G. Gielen, “Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization,” in Proc. - ISCAS, pp. 1298–1301, May 2005.
R. Rutenbar, G. Gielen, and J. Roychowdhury, “Hierarchical modeling, optimization, and synthesis for system-level analog and RF designs,” Proceedings of the IEEE 95(3), pp. 640–669, March 2007.
P. Mandal and V. Visvanathan, “Macromodeling of the A.C. characteristics of CMOS opamps,” in Proc. International Conference on Computer-Aided Design., 7, pp. 334–340, Nov. 1993.
France, Michel Mendes and Henaut, Alain, “Art, therefore entropy,” Leonardo 27(3), pp. 219–221, 1994.
A. Denis and F.Cremoux, “Using the entropy of curves to segment a time or spatial series,” in Mathematical Geology, 33, pp. 899–914, Nov. 2002.
M. Kutner, C. Nachtsheim, W. Wasserman, and J. Neter, Applied Linear Regression Models, McGraw-Hill/Irwin, 2003.
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., 2000.
J. Rawlings, S. Panstula, and D. Dickey, Applied Regression Analysis : A Research Tool, Springer, 2001.
J. M. Cohn, Analog Device-Level Layout Automation, Kluwer Academic Publishers, Norwell, MA, USA, 2000.
T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to algorithms, MIT Press, 2001.
A. Pradhan and R. Vemuri, “On the use of hash tables for efficient analog circuit synthesis,” in Proceedings of the International Conference on VLSI Design, Jan 2008.
S. Arya, D. M. Mount, N. S. Netanyahu, R. Silverman, and A. Y. Wu, “An optimal algorithm for approximate nearest neighbor searching in fixed dimensions,” Journal of the ACM 45(6), pp. 891–923, 1998.
A. Pradhan and R. Vemuri, “Fast analog circuit synthesis using sensitivity based near neighbor searches,” in Proceedings of the conference on Design Automation and Test in Europe (To Appear), Mar 2008.
Author information
Authors and Affiliations
Corresponding authors
Rights and permissions
Copyright information
© 2009 Springer-Verlag US
About this chapter
Cite this chapter
Pradhan, A., Vemuri, R. (2009). Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis. In: VLSI-SoC: Advanced Topics on Systems on a Chip. IFIP International Federation for Information Processing, vol 291. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-89558-1_8
Download citation
DOI: https://doi.org/10.1007/978-0-387-89558-1_8
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-89557-4
Online ISBN: 978-0-387-89558-1
eBook Packages: Computer ScienceComputer Science (R0)