This paper presents performance comparisons between two multipliers architectures. The first architecture consists of a pure array multiplier that was modified to handle the sign bits in 2’s complement and uses a radix-4 encoding to reduce the partial product lines. The second architecture implemented was the widely used Modified Booth multiplier. We describe a design methodology to physically implement these architectures in a pipelined and non-pipelined form, obtaining area, power consumption and delay results. Up to now only results at the logic level were presented in previous work. The performance of pipelined array architecture is compared with the pipelined Modified Booth. We compare the physical implementations in terms of area, power and delay. The results show that the new pipelined array multiplier can be significantly more efficient, with close to 16% power savings and 55% power savings when considering non-pipelined architectures.
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Callaway, T.; Swartzlander, E. Optimizing multipliers for WSI. In Fifth Annual IEEE International Conference on Wafer Scale Integration, pages 85-94, 1993.
Cherkauer, B; Friedman, E. A Hybrid Radix-4/Radix-8 Low Power, High Speed Multiplier Architecture for Wide Bit Widths. In IEEE International Symposium on Circuits and Systems, volume 4, pages 53-56, 1996.
Wang, Y.; Jiang, Y.; Sha, E. On Area-Efficient Low Power Array Multipliers. In the 8th IEEE International Conference on Electronics, Circuits and Systems, pages 1429-1432, 2001
Costa E. da; Monteiro J., and S. Bampi. A New Architecture for 2's Complement Gray Encoded Array Multiplier. In Proceedings Symposium on Integrated Circuits and Systems, pages 14-19, 2002.
Costa, E., Monteiro, J., Bampi, S. A New Architecture for Signed Radix-2m Pure Array Multiplier. IEEE ICCD, September 2002.
Costa, E., Bampi, S., Monteiro, J. A New Pipelined Array Architecture for Signed Multiplication. 16th SBCCI, September 2003.
Gallagher, W. and Swartzlander, E. High Radix Both Multipliers Using Reduced Area Adder Trees. In Twenty-Eighth Asilomar Conference on Signals, Systems and Computers, volume I, pages 545-549, 1994.
Genderen, A. J. SLS: An Efficient Switch-Level Timing Simulator Using Min-Max Voltage Waveforms. Proceedings of VLSI Conference, pages 79-88, 1989.
Goto, G.; et al. A 4.1-ns Compact 54 x 54-b Multiplier Utilizing Sign-Select Booth Encoders. IEEE Journal of Solid-State Circuits, 32:1676-1682, 1997.
Goldovsky and et al. Design and Implementation of a 16 by 16 Low Power Two's Complement Multiplier. In IEEE International Symposium on Circuits and Systems, volume 5, pages 345-348, 2000.
Hwang, K. Computer Arithmetic -Principles, Architecture and Design. John Wiley & Sons, 1979.
Synopsys PrimeTime Design Reference Manual, 2004.
Khater, I.; Bellaouar, A.; Elmasry, M. Circuit Techniques for CMOS Low-Power, High-Performance Multipliers. IEEE Journal of Solid-State Circuits, 31:1535-1546, 1996.
Yano, K. andet al. A 3.8-ns CMOS 16 x 16-b Multiplier Using Complementary Pass Transistor Logic. Journal of solid-State Circuits, 25:388-395, 1990.
Moraes, F. A Virtual CMOS Library Approach for Fast Layout Synthesis. In: IFIP TC10 WG10.5 International Conference on Very Large Scale Integration, 10, pages 415-426, 1999.
Seidel, P., Mcfearin, L. and Matula, D. Binary Multiplication Radix-32 and Radix-256. In 15th Symposium on Computer Arithmetic, pages 23-32, 2001.
Sentovich, E. and et al. SIS: A System for Sequential Circuit Synthesis. Technical report, University of California at Berkeley, UCB/ERL -Memorandum n° M92/41, 1992.
Wallace, C. A Suggestion for a Fast Multiplier. IEEE Transactions on Electronic Computers, 13:14-17, 1964.
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de Oliveira, L.L. et al. (2007). A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. In: Reis, R., Osseiran, A., Pfleiderer, HJ. (eds) Vlsi-Soc: From Systems To Silicon. IFIP International Federation for Information Proc, vol 240. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-73661-7_3
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