Abstract
Memory represents a major bottleneck in embedded systems. For multimedia applications bulky of data in these embedded systems require shared memory. But the integration of this kind of memory implies some architectural modifications and code transformations. And no automatic tool exists allowing designers to integrate shared memory in the SoC design flow. In this work, we present a systematic approach for the design of shared memory architectures for application-specific multiprocessor systems-on-chip. This work focuses on the code-transformations related to the integration of a shared memory.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35597-9_40
Chapter PDF
Similar content being viewed by others
References
A. Baghdadi, D. Lyonnard, N-E. Zergainoh, A.A. Jerraya, "An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC", DATE'2001.
F. Cathoor and al, Custom Memory Management Methodology, Kluwer Academic Publishers, 1998.
D. Culler, J.P. Singh, A. Gupta, "Parallel computer architecture: A Hardware/Software approach", Maurgan Kauffman publishers, August 1998.
A. Fraboulet, G. Huard, A. Mignotte, "Loop Alignment for Memory Accesses Optimization", Proc. of ISSS 1999.
F. Gharsalli, S. Meftali, F. Rousseau, A.A. Jerraya, " Automatic Generation of Embedded Memory Wrapper", Proc. of DAC 2002.
J. Hennessy, M. Heinrich, A. Gupta, "Cache-Coherent Distributed Shared Memory: Perspectives on Its Development and Future Challenges", Special issue on distributed Shared-Memory Systems, Match 1999.
IBM, Inc. "28.4G Packet Rooting Switch", Networking Technology Data sheets, http://www.chi i)s.ibm.com/techlib/products/commun/datasheets.html
D. Kulkami, M. Stumm, "Linear loop transformations in optimizing compilers for parallel machines" in The australian computer journal, pp. 41 - 50, May 1995.
S. Meftali, F. Gharsalli, F. Rousseau, A.A. Jerraya, "An Optimal Memory Allocation for Application-Specific Multiprocessor System-on-Chip", Proc. of ISSS 2001.
P. R. Panda, N. Dutt, A. Nicolau, Memory Issues in Embedded Systems-on-chip: Optimization and exploration, Kluwer Academic Publishers, 1999.
S. Rixner, W. J. Daily, U. J. Kapasi, P. Mattson, J. D. Owens, "Memory Access Scheduling", Proc. of ISCA 2000.
K. Svarstad, G. Nicolescu, A. A. Jerraya, "A Model for Describing Communication between Aggregate Objects in the Specification and Design of Embedded Systems", DATE'2001.
M. Wolf, "improving locality and parallelism in nested loops", Ph.D dissertation, Stanford University, USA, August 92.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 IFIP International Federation for Information Processing
About this chapter
Cite this chapter
Meftali, S., Gharsalli, F., Rousseau, F., Jerraya, A.A. (2002). Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory. In: Robert, M., Rouzeyre, B., Piguet, C., Flottes, ML. (eds) SOC Design Methodologies. IFIP — The International Federation for Information Processing, vol 90. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35597-9_17
Download citation
DOI: https://doi.org/10.1007/978-0-387-35597-9_17
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-6530-4
Online ISBN: 978-0-387-35597-9
eBook Packages: Springer Book Archive