Abstract
This paper investigates specification and verification of synchronous circuits using Dill (Digital Logic in Lotos). After an overview of the Dill approach, the paper focuses on the characteristics of synchronous circuits. A more constrained model is presented for specifying digital components and verifying them. Two standard benchmark circuits are specified using this new model, and analysed by the Cadp toolset (Cæsar/Aldébaran Development Package).
Chapter PDF
Similar content being viewed by others
References
A. Bouajjani, J. C. Fernandez, et al. Safety for branching time semantics. In Automata, Languages and Programming, LNCS 510, pages 76–92. Springer-Verlag, Berlin, 1991.
R. Boulton, M. J. C. Gordon et al. The HOL verification of ELLA designs. TR 199, University of Cambridge Computer Laboratory, Aug. 1990.
G. Chehaibar, H. Garavel, et al. Specification and verification of the PowerScale bus arbitration protocol: An industrial experiment with LOTOS. TR 2958, INRIA, Le Chesnay, Aug. 1996.
R. De Nicola and F. Vaandrager. Action versus state based logics for transition systems. In Semantics for Systems of Concurrent Processes, LNCS 469, pages 407–419. Springer-Verlag, Berlin, 1990.
C. Delgado Kloos, T. de Miguel et al. VI-DL generation from a timed extension of the formal description technique LOTOS with the FORMAT project. Microprocessing and Microprogramming, 38: 589–596, 1993.
M. Faci and L. M. S. Logrippo. Specifying hardware in LOTOS. In Proc. Computer Hardware Description Languages and Their Applications XI, pages 305–312. North-Holland, Amsterdam, Apr. 1993.
J.-C. Fernandez, H. Garavel, et al. CADP (Cmsar/Aldébaran development package): A protocol validation and verification toolbox. In R. Alur and T. A. Henzinger, editors, Proc. Computer-Aided Verification VIII, LNCS 1102, pages 437–440. Springer-Verlag, Berlin, Aug. 1996.
K. Fisler and R. P. Kurshan. Verifying VI-DL designs with COSPAN. In Formal Hardware Verification Methods and Systems in Comparison, LNCS 1287, pages 206–247. Springer-Verlag, Berlin, 1997.
C. A. R. Hoare and M. J. C. Gordon, editors. Mechanized Reasoning and Hardware Design. Prentice Hall, Englewood Cliffs, 1992.
IEEE. VHSIC Hardware Design Language. IEEE 1076. Institution of Electrical and Electronic Engineers Press, New York, 1993.
IEEE IEEE Standard Hardware Design Language based on the Verilog Hardware Description Language. IEEE 1364. Institution of Electrical and Electronic Engineers Press, New York, 1995.
ISO/IEC. Information Processing Systems — Open Systems Interconnection — LOTOS - A Formal Description Technique based on the Temporal Ordering of Observational Behaviour. ISO/IEC 8807. International Organization for Standardization, Geneva, 1989.
ISO/IEC. Information Processing Systems — Open Systems Interconnection — Enhancements to LOTOS. International Organization for Standardization, Geneva, Apr. 1998.
Ji He and K. J. Turner. Extended DILL: Digital logic with LOTOS. TR CSM-142, Computing Science and Mathematics, University of Stirling, UK, Nov. 1997.
Ji He and K. J. Turner. DILL (Digital Logic in Lows) translator. ,http://www.cs.stir.ac.uk/—kjt/software/dill.html Jan. 1998.
Ji He and K. J. Turner. Timed DILL: Digital logic with LOTOS. TR CSM-145, Computing Science and Mathematics, University of Stirling, Apr. 1998.
Ji He and K. J. Turner. Modelling and verifying synchronous circuits in DILL. TR CSM-152, Computing Science and Mathematics, University of Stirling, Feb. 1999.
G. Jones and M. Sheeran. Circuit design in Ruby. In J. Staunstrup, editor, Formal Methods For VLSI Design, pages 13–70. Elsevier Science Publishers, Amsterdam, 1990.
L. Léonard and G. Leduc. An introduction to ET-LOTOS for the description of time-sensitive systems. Computer Networks and ISDN Systems, 28: 271–292, May 1996.
G. A. McCaskill and G. J. Milne. Sequential circuit analysis with a BDD based process algebra system. TR HDV-25–93, Computer Science, University of Strathclyde, Jan. 1993.
G. J. Milne. The Formal Specification and Verification of Digital Systems. McGraw-Hill, New York, 1994.
L. Sanchez Fernandez, M. L. López et al. Co-design at work: The Ethernet bridge case study. Current Issues in Electronic Modelling, 8, Apr. 1996.
M. Sighireanu and R. Mateescu. Validation of the link layer protocol of the IEEE-1394 serial bus (`Firewire’): An experiment with E-LOTOS. TR 3172, Institut National de Recherche en Informatique et Automatique, Le Chesnay, May 1997.
J. Staunstrup and T. Kropf. IFIP WG10.5 benchmark circuits. http://goethe.ira.uka.de/hvg/benchmarks.html, July 1996.
K. J. Turner and R. O. Sinnott. DILL: Specifying digital logic in LOTOS. In R. L. Tenney, P. D. Amer, and M. Ü. Uyar, editors, Proc.Formal Description Techniques VI, pages 7186. North-Holland, Amsterdam, 1994.
R. J. van Glabbeek and W. P. Weijland. Branching time and abstraction in bisimulation. TR CS R8911, Centrum voor Wiskunde en Informatica, Amsterdam, 1989.
K. Yasumoto, A. Kitajima et al. Hardware synthesis from protocol specifications in LOTOS. In S. Budkowski, E. Najm, and A. Cavalli, editors, Proc. Formal Description Techniques XI/Protocol Specification, Testing and Verification XVIII. Chapman-Hall, London, 1998.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
He, J., Turner, K.J. (1999). Specification and Verification of Synchronous Hardware using LOTOS. In: Wu, J., Chanson, S.T., Gao, Q. (eds) Formal Methods for Protocol Engineering and Distributed Systems. PSTV FORTE 1999 1999. IFIP Advances in Information and Communication Technology, vol 28. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35578-8_17
Download citation
DOI: https://doi.org/10.1007/978-0-387-35578-8_17
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-5270-0
Online ISBN: 978-0-387-35578-8
eBook Packages: Springer Book Archive