Abstract
A new controller architecture is presented which can handle multiple threads efficiently without state explosions. The architecture is based upon a ROM, where the address decoders are replaced by latches on each row, which makes it possible activating more rows (states) at the same time. The extra logic for controlling the control flow is minimal.
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© 1995 IFIP International Federation for Information Processing
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Hilderink, H.A., Jess, J.A.G. (1995). ROM-based Multi Thread Controller. In: Saucier, G., Mignotte, A. (eds) Logic and Architecture Synthesis. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34920-6_16
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DOI: https://doi.org/10.1007/978-0-387-34920-6_16
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-5041-2923-7
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