Abstract
Symbolic trajectory evaluation (STE) is a method for efficient circuit verification [1]. In [2] a set of inference rules was introduced for combining STE results. These inference rules were also proven sound. In this paper we show that, with one additional inference rule, the inference system is complete. Here, complete means that any formula A⇒C, that is valid in every model satisfying some collection Φ of STE assertions, can be derived from Φ by a finite applications of the inference rules. The completeness proof is based on the method of model construction — given Φ, a most general circuit model (in which every assertion in Φ holds) can be generated.
This research was supported, in part, by operating grants OGPO 109688 and OGPO 046196 from the Natural Sciences and Engineering Research Council of Canada, fellowships from the Province of British Columbia Advanced Systems Institute, and by research contract 92-DJ-295 from the Semiconductor Research Corporation.
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Seger, C.-J., and Bryant, R. Formal verification of digital circuits by symbolic evaluation of partially-ordered trajectories. Tech. Rep. Technical Report 93-8, The Computer Science Department, The University of British Columbia, The Computer Science Department, The University of B.C. Vancouver B.C. V6T 1Z4, 1993.
Hazelhurst, S., and Seger, C.-J. A simple theorem prover based on symbolic trajectory evaluation and obdds. Tech. Rep. Technical Report 93-41, The Computer Science Department, The University of British Columbia, The Computer Science Department, The University of B.C. Vancouver B.C. V6T 1Z4, 1993. (An abridged version of this work appears in this proceedings).
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© 1994 Springer-Verlag Berlin Heidelberg
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Zhu, Z., Seger, CJ. (1994). The completeness of a hardware inference system. In: Dill, D.L. (eds) Computer Aided Verification. CAV 1994. Lecture Notes in Computer Science, vol 818. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58179-0_62
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DOI: https://doi.org/10.1007/3-540-58179-0_62
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