Abstract
This paper describes a tool framework and techniques for combining serialisation and recon.guration to produce efficient designs. Convolver and matrix multiplier designs are examined. Several optimisation techniques, such as restructuring and pipeline morphing, are presented with an analysis of their impact on performance and resource usage. The proposed techniques do not require the basic processing element to be modified. An estimate of the performance of the serial designs is given when mapped using distributed arithmetic and constant multiplier cores onto a Xilinx Virtex FPGA.
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References
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© 2000 Springer-Verlag Berlin Heidelberg
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Derbyshire, A., Luk, W. (2000). Combining Serialisation and Reconfiguration for FPGA Designs. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_68
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DOI: https://doi.org/10.1007/3-540-44614-1_68
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