Abstract
For static CMOS Clock-Gating is a well-known method to decrease dynamic losses. In order to reduce the static power consumption caused by leakage currents, Power-Gating has been introduced. This paper presents for the first time Clock-Gating and Power-Gating in Adiabatic Logic. As the oscillator signal is both the power and the clock in Adiabatic Logic, a Power-Clock Gating is implemented using a switch to detach the adiabatic logic block from the oscillator. Depending on the technology the optimum switch topology and dimension is discussed. This paper shows that a boosted n-channel MOSFET as well as a transmission gate are good choices as a switch. Adiabatic losses are reduced greatly by shutting down idle adiabatic circuit blocks with Power-Clock Gating.
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Teichmann, P., Fischer, J., Henzler, S., Amirante, E., Schmitt-Landsiedel, D. (2005). Power-Clock Gating in Adiabatic Logic Circuits. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_65
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DOI: https://doi.org/10.1007/11556930_65
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
Online ISBN: 978-3-540-32080-7
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