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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings

  • Vassilis Paliouras
  • Johan Vounckx
  • Diederik Verkest

Part of the Lecture Notes in Computer Science book series (LNCS, volume 3728)

Table of contents

  1. Front Matter
  2. Session 1: Low-Power Processors

    1. Fernando Castro, Daniel Chaver, Luis Pinuel, Manuel Prieto, Michael C. Huang, Francisco Tirado
      Pages 1-9
    2. David Rios-Arambula, Aurélien Buhrig, Marc Renaudin
      Pages 10-18
    3. Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat
      Pages 19-29
    4. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
      Pages 30-39
    5. Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
      Pages 40-48
  3. Session 2: Code Optimization for Low-Power

    1. Meuse N. O. Junior, Paulo Maciel, Ricardo Lima, Angelo Ribeiro, Cesar Oliveira, Adilson Arcoverde et al.
      Pages 49-58
    2. Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis
      Pages 59-68
    3. Jose M. Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor, Francisco Tirado, J. M. Mendias
      Pages 69-78
  4. Session 3: High-Level Design

    1. Martin Palkovic, Erik Brockmeyer, P. Vanbroekhoven, Henk Corporaal, Francky Catthoor
      Pages 89-98
    2. Ali Manzak
      Pages 99-106
    3. Bert Geelen, Gauthier Lafruit, V. Ferentinos, R. Lauwereins, Diederik Verkest
      Pages 107-116
    4. Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
      Pages 117-126
  5. Session 4: Telecommunications and Signal Processing

    1. Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel
      Pages 146-155
    2. Hyun Ho Kim, Jung Hee Kim, Yong-hyeog Kang, Young Ik Eom
      Pages 156-165
    3. Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon
      Pages 166-176
    4. Th. Giannopoulos, Vassilis Paliouras
      Pages 177-186
  6. Session 5: Low-Power Circuits

  7. Session 6: System-on-Chip Design

    1. Tajana Simunic, Kresimir Mihic, Giovanni De Micheli
      Pages 237-246
    2. Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis
      Pages 247-256
    3. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
      Pages 257-266
    4. Mariagrazia Graziano, Cristiano Forzan, Davide Pandini
      Pages 267-276
  8. Session 7: Busses and Interconnections

    1. Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
      Pages 277-285
    2. Crescenzo D’Alessandro, Delong Shang, Alex Bystrov, Alex Yakovlev
      Pages 286-296
    3. Ashutosh Chakraborty, Enrico Macii, Massimo Poncino
      Pages 297-307
    4. Giorgos Dimitrakopoulos, Dimitris Nikolos
      Pages 308-317
    5. Jin Shi, Yici Cai, Xianlong Hong, Shelton X. D. Tan
      Pages 318-328
  9. Session 8: Modeling

    1. Gregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo
      Pages 329-336
    2. Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz de Clavijo, David Guerrero Martos, E. Ostúa et al.
      Pages 337-347
    3. Jose L. Rosselló, Sebastià Bota, Jaume Segura
      Pages 348-354
    4. Massimo Alioto, Gaetano Palumbo, Massimo Poli
      Pages 355-363
    5. Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark
      Pages 364-373
  10. Session 9: Design Automation

    1. Didier Van Reeth, Georges Gielen
      Pages 374-381
    2. Eduardo Tavares, Raimundo Barreto, Paulo Maciel, Meuse Oliveira Jr., Adilson Arcoverde, Gabriel Alves Jr. et al.
      Pages 382-392
    3. Miodrag Vujkovic, David Wadkins, Carl Sechen
      Pages 393-403
    4. Radu Zlatanovici, Borivoje Nikolić
      Pages 404-414
    5. Siobhán Launders, Colin Doyle, Wesley Cooper
      Pages 415-424
  11. Session 10: Low-Power Techniques

    1. Paulino Ruiz de Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, E. Ostúa et al.
      Pages 425-435
    2. Tezaswi Raja, Vishwani D. Agrawal, Michael Bushnell
      Pages 436-445
    3. Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
      Pages 446-455
  12. Session 11: Memory and Register Files

    1. K. Patel, L. Benini, Enrico Macii, Massimo Poncino
      Pages 466-476

About these proceedings

Introduction

Welcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on “Traveling the Wild Frontier of Ulta Low-Power Design”, Dr. Sung Bae Park, S- sung, gave a presentation on “DVL (Deep Low Voltage): Circuits and Devices”, Prof.

Keywords

Automat automation communication integrated circuit modeling optimization processor simulation system on chip (SoC) telecommunications

Editors and affiliations

  • Vassilis Paliouras
    • 1
  • Johan Vounckx
    • 2
  • Diederik Verkest
    • 3
  1. 1.Electrical and Computer Engineering DepartmentUniversity of PatrasGreece
  2. 2.IMECHeverleeBelgium
  3. 3.Dept. of Electrical EngineeringVUBBrusselsBelgium

Bibliographic information

  • DOI https://doi.org/10.1007/11556930
  • Copyright Information Springer-Verlag Berlin Heidelberg 2005
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-540-29013-1
  • Online ISBN 978-3-540-32080-7
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site